參數(shù)資料
型號： MFRC50001T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡
英文描述： Highly integrated ISO-IEC 14443 A reader IC
封裝： MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,;
文件頁數(shù)： 7/110頁
文件大?。?/td> 841K
代理商： MFRC50001T
MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
7 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
9. Functional description
9.1 Digital interface
9.1.1
Overview of supported microprocessor interfaces
The MFRC500 supports direct interfacing to various 8-bit microprocessors. Alternatively,
the MFRC500 can be connected to a PC’s Enhanced Parallel Port (EPP).
Table 4
shows
the parallel interface signals supported by the MFRC500.
Table 4.
Bus control signals
9.1.2
Automatic microprocessor interface detection
After a Power-On or Hard reset, the MFRC500 resets the parallel microprocessor
interface mode and detects the microprocessor interface type.
The MFRC500 identifies the microprocessor interface using the logic levels on the control
pins. This is performed using a combination of fixed pin connections and the dedicated
Initialization routine (see
Section 9.7.4 on page 25
).
Supported microprocessor and EPP interface signals
Bus
Separated address
and data bus
Separated read and
write strobes
address
Multiplexed address and data bus
control
NRD, NWR, NCS
NRD, NWR, NCS, ALE
A0, A1, A2
AD0, AD1, AD2, AD3, AD4, AD5
data
D0 to D7
AD0 to AD7
Common read and write
strobe
control
R/NW, NDS, NCS
R/NW, NDS, NCS, AS
address
A0, A1, A2
AD0, AD1, AD2, AD3, AD4, AD5
data
D0 to D7
AD0 to AD7
Common read and write
strobe with handshake
(EPP)
control
-
nWrite, nDStrb, nAStrb, nWait
address
-
AD0, AD1, AD2, AD3, AD4, AD5
data
-
AD0 to AD7
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