參數(shù)資料
型號(hào): MFRC50001T
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Highly integrated ISO-IEC 14443 A reader IC
封裝: MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,;
文件頁(yè)數(shù): 65/110頁(yè)
文件大?。?/td> 841K
代理商: MFRC50001T
MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
65 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
10.5.8.4
Reserved register 3Bh
Table 121. Reserved register (address: 3Bh) reset value: xxxx xxxxb, xxh bit allocation
Bit
7
6
5
Symbol
Access
Remark:
This register is reserved for future use.
10.5.8.5
Reserved register 3Ch
Table 122. Reserved register (address: 3Ch) reset value: xxxx xxxxb, xxh bit allocation
Bit
7
6
5
Symbol
Access
Remark:
This register is reserved for future use.
10.5.8.6
TestDigiSelect register
Selects digital test mode.
Table 123. TestDigiSelect register (address: 3Dh) reset value: xxxx xxxxb, xxh bit allocation
Bit
7
6
5
Symbol
SignalToMFOUT
Access
W
Table 124. TestDigiSelect register bit descriptions
Bit
Symbol
7
SignalToMFOUT
4
3
2
1
0
xxxxxxxx
W
4
3
2
1
0
xxxxxxxx
W
4
TestDigiSignalSel[6:0]
W
3
2
1
0
Value
1
Description
overrules the MFOUTSelect[2:0] setting and routes the
digital test signal defined with the TestDigiSignalSel[6:0]
bits to pin MFOUT
MFOUTSelect[2:0] defines the signal on pin MFOUT
selects the digital test signal to be routed to pin MFOUT.
Refer to
Section 15.2.3 on page 97
for detailed
information. The following lists the signal names for the
TestDigiSignalSel[6:0] addresses:
s_data
s_valid
s_coll
s_clock
rd_sync
wr_sync
int_clock
0
-
6 to 0
TestDigiSignalSel[6:0]
F4h
E4h
D4h
C4h
B5h
A5h
96h
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