參數(shù)資料
型號(hào): MFRC50001T
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Highly integrated ISO-IEC 14443 A reader IC
封裝: MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,;
文件頁(yè)數(shù): 44/110頁(yè)
文件大?。?/td> 841K
代理商: MFRC50001T
MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
44 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
10.5.1.2
Command register
Starts and stops the command execution.
Table 35.
Bit
Symbol
Access
Table 36.
Bit
7
10.5.1.3
FIFOData register
Input and output of the 64 byte FIFO buffer.
Table 37.
Bit
Symbol
Access
Table 38.
Bit
7 to 0
Command register (address: 01h) reset value: x000 0000b, x0h bit allocation
7
6
5
IFDetectBusy
0
R
R
4
3
2
1
0
Command[5:0]
D
Command register bit descriptions
Symbol
Value
IFDetectBusy
0
1
0
-
Command[5:0]
-
Description
shows the status of interface detection logic
interface detection finished successfully
interface detection ongoing
reserved
activates a command based on the Command code.
Reading this register shows which command is being
executed.
6
5 to 0
FIFOData register (address: 02h) reset value: xxxx xxxxb, xxh bit allocation
7
6
5
FIFOData[7:0]
4
3
2
1
0
D
FIFOData register bit descriptions
Symbol
Description
FIFOData[7:0]
data input and output port for the internal 64-byte FIFO buffer. The FIFO
buffer acts as a parallel in to parallel out converter for all data streams.
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