參數(shù)資料
型號(hào)： MFRC50001T
廠商： NXP Semiconductors N.V.
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Highly integrated ISO-IEC 14443 A reader IC
封裝： MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,;
文件頁(yè)數(shù)： 16/110頁(yè)
文件大?。?/td> 841K
代理商： MFRC50001T
MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
16 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
(1)
The LoAlert flag bit is set to logic 1 when the FIFOLevel register’s WaterLevel[5:0] bits or
less are stored in the FIFO buffer. The trigger is generated by
Equation 2
:
(2)
9.3.4
FIFO buffer registers and flags
Table 14
shows the related FIFO buffer flags in alphabetic order.
Table 14.
Flags
FIFOLength[6:0]
FIFOOvfl
FlushFIFO
HiAlert
HiAlertIEn
HiAlertIRq
LoAlert
LoAlertIEn
LoAlertIRq
WaterLevel[5:0]
9.4 Interrupt request system
The MFRC500 indicates interrupt events by setting the PrimaryStatus register bit IRq (see
Section 10.5.1.4 “PrimaryStatus register” on page 45
) and activating pin IRQ. The signal
on pin IRQ can be used to interrupt the microprocessor using its interrupt handling
capabilities ensuring efficient microprocessor software.
9.4.1
Interrupt sources overview
Table 15
shows the integrated interrupt flags, related source and setting condition. The
interrupt TimerIRq flag bit indicates an interrupt set by the timer unit. Bit TimerIRq is set
when the timer decrements from one down to zero (bit TAutoRestart disabled) or from one
to the TReLoadValue[7:0] with bit TAutoRestart enabled.
Bit TxIRq indicates interrupts from different sources and is set as follows:
the transmitter automatically sets the bit TxIRq interrupt when it is active and its state
changes from sending data to transmitting the end of frame pattern
the CRC coprocessor sets the bit TxIRq after all data from the FIFO buffer has been
processed indicated by bit CRCReady = logic 1
when EEPROM programming is finished, the bit TxIRq is set and is indicated by bit
E2Ready = logic 1
The RxIRq flag bit indicates an interrupt when the end of the received data is detected.
The IdleIRq flag bit is set when a command finishes and the content of the Command
register changes to Idle.
HiAlert
64
FIFOLength
–
(
)
WaterLevel
≤
=
LoAlert
FIFOLength
WaterLevel
≤
=
Associated FIFO buffer registers and flags
Register name
FIFOLength
ErrorFlag
Control
PrimaryStatus
InterruptEn
InterruptRq
PrimaryStatus
InterruptEn
InterruptRq
FIFOLevel
Bit
6 to 0
4
0
1
1
1
0
0
0
5 to 0
Register address
04h
0Ah
09h
03h
06h
07h
03h
06h
07h
29h
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