參數(shù)資料
型號(hào): MFRC50001T
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Highly integrated ISO-IEC 14443 A reader IC
封裝: MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,;
文件頁數(shù): 43/110頁
文件大小: 841K
代理商: MFRC50001T
MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
43 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
10.5 Register descriptions
10.5.1
Page 0: Command and status
10.5.1.1
Page register
Selects the page register.
Table 33.
Table 34.
Bit
7
TX1RFEn
TX2Cw
TX2Inv
TX2RFEn
TxCRCEn
TxIEn
TxIRq
TxLastBits[2:0]
UsePageSelect
TxControl
TxControl
TxControl
TxControl
ChannelRedundancy
InterruptEn
InterruptRq
BitFraming
Page
0
3
3
1
2
4
4
2 to 0
7
11h
11h
11h
11h
22h
06h
07h
0Fh
00h, 08h, 10h, 18h, 20h, 28h, 30h
and 38h
29h
1Ah
WaterLevel[5:0]
ZeroAfterColl
FIFOLevel
DecoderControl
5 to 0
5
Table 32.
Flag(s)
MFRC500 register flags overview
…continued
Register
Bit
Address
Page register (address: 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h)
reset value: 1000 0000b, 80h bit allocation
7
6
UsePageSelect
R/W
Bit
Symbol
Access
5
4
3
2
1
0
0000
R/W
PageSelect[2:0]
R/W
R/W
R/W
Page register bit descriptions
Symbol
UsePageSelect 1
Value
Description
the value of PageSelect[2:0] is used as the register address
A5, A4, and A3. The LSBs of the register address are
defined using the address pins or the internal address latch,
respectively.
the complete content of the internal address latch defines
the register address. The address pins are used as
described in
Table 5 on page 8
.
reserved
when UsePageSelect = logic 1, the value of PageSelect is
used to specify the register page (A5, A4 and A3 of the
register address)
0
6 to 3
2 to 0
0000
PageSelect[2:0] -
-
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