參數(shù)資料
型號： MFRC50001T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Highly integrated ISO-IEC 14443 A reader IC
封裝： MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,;
文件頁數(shù)： 25/110頁
文件大?。?/td> 841K
代理商： MFRC50001T
MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
25 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
9.7 StartUp phase
The events executed during the StartUp phase are shown in
Figure 8
.
9.7.1
Hard power-down phase
The hard power-down phase is active during the following cases:
a Power-On Reset (POR) caused by power-up on pins DVDD or AVDD activated
when V
DDD
or V
DDA
is below the relevant analog/digital reset threshold.
a HIGH-level on pin RSTPD which is active while pin RSTPD is HIGH. The HIGH level
period on pin RSTPD must be at least 100
μ
s (t
PD
≥
100
μ
s). Shorter phases will not
necessarily result in the reset phase (t
reset
). The rising or falling edge slew rate on pin
RSTPD is not critical because pin RSTPD is a Schmitt trigger input.
9.7.2
Reset phase
The reset phase automatically follows the Hard power-down. Once the oscillator is
running stably, the reset phase takes 512 clock cycles. During the reset phase, some
register bits are preset by hardware. The respective reset values are given in the
description of each register (see
Section 10.5 on page 43
).
Remark:
When the internal oscillator is used, time (t
osc
) is required for the oscillator to
become stable. This is because the internal oscillator is supplied by V
DDA
and any clock
cycles will not be detected by the internal logic until V
DDA
is stable.
9.7.3
Initialization phase
The initialization phase automatically follows the reset phase and takes 128 clock cycles.
During the initializing phase the content of the EEPROM blocks 1 and 2 is copied into the
register subaddresses 10h to 2Fh (see
Section 9.2.2 on page 11
).
Remark:
During the production test, the MFRC500 is initialized with default configuration
values. This reduces the microprocessor’s configuration time to a minimum.
9.7.4
Initializing the parallel interface type
A different initialization sequence is used for each microprocessor. This enables detection
of the correct microprocessor interface type and synchronization of the microprocessor’s
and the MFRC500’s start-up. See
Section 9.1.3 on page 8
for detailed information on the
different connections for each microprocessor interface type.
During StartUp phase, the command value is set to 3Fh once the oscillator attains clock
frequency stability at an amplitude of > 90 % of the nominal 13.56 MHz clock frequency. At
the end of the initialization phase, the MFRC500 automatically switches to idle and the
command value changes to 00h.
Fig 8.
The StartUp procedure
001aak613
StartUp phase
states
t
RSTPD
t
reset
t
init
Hard power-
down phase
Reset phase
Initialising
phase
ready
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