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| 型號(hào)： | MFRC50001T |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Highly integrated ISO-IEC 14443 A reader IC |
| 封裝： | MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,; |
| 文件頁數(shù)： | 17/110頁 |
| 文件大?。?/td> | 841K |
| 代理商： | MFRC50001T |
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MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
17 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
When the FIFO buffer reaches the HIGH-level indicated by the WaterLevel[5:0] value (see
Section 9.3.3 on page 15
) and bit HiAlert = logic 1, then the HiAlertIRq flag bit is set to
logic 1.
When the FIFO buffer reaches the LOW-level indicated by the WaterLevel[5:0] value (see
Section 9.3.3
and bit LoAlert = logic 1, then LoAlertIRq flag bit is set to logic 1.
Table 15.
Interrupt flag
TimerIRq
TxIRq
9.4.2
Interrupt request handling
9.4.2.1
Controlling interrupts and getting their status
The MFRC500 informs the microprocessor about the interrupt request source by setting
the relevant bit in the InterruptRq register. The relevance of each interrupt request bit as
source for an interrupt can be masked by the InterruptEn register interrupt enable bits.
If an interrupt request flag is set to logic 1 (showing that an interrupt request is pending)
and the corresponding interrupt enable flag is set, the PrimaryStatus register IRq flag bit is
set to logic 1. Different interrupt sources can activate simultaneously and because of this,
all interrupt request bits are OR’ed, coupled to the IRq flag and then forwarded to pin IRQ.
9.4.2.2
Accessing the interrupt registers
The interrupt request bits are automatically set by the MFRC500’s internal state
machines. In addition, the microprocessor can also set or clear the interrupt request bits
as required.
A special implementation of the InterruptRq and InterruptEn registers enables changing
an individual bit status without influencing any other bits. If an interrupt register is set to
logic 1, bit SetIxx and the specific bit must both be set to logic 1 at the same time. Vice
versa, if a specific interrupt flag is cleared, zero must be written to the SetIxx and the
interrupt register address must be set to logic 1 at the same time.
If a content bit is not changed during the setting or clearing phase, zero must be written to
the specific bit location.
Interrupt sources
Interrupt source
timer unit
transmitter
CRC coprocessor
EEPROM
Trigger action
timer counts from 1 to 0
a data stream, transmitted to the card, ends
all data from the FIFO buffer has been processed
all data from the FIFO buffer has been
programmed
a data stream, received from the card, ends
command execution finishes
FIFO buffer is full
FIFO buffer is empty
RxIRq
IdleIRq
HiAlertIRq
LoAlertIRq
receiver
Command register
FIFO buffer
FIFO buffer
Table 16.
Register
InterruptEn
InterruptRq
Interrupt control registers
Bit 7
SetIEn
SetIRq
Bit 6
reserved
reserved
Bit 5
TimerIEn
TimerIRq
Bit 4
TxIEn
TxIRq
Bit 3
RxIEn
RxIRq
Bit 2
IdleIEn
IdleIRq
Bit 1
HiAlertIEn
HiAlertIRq
Bit 0
LoAlertIEn
LoAlertIRq
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