參數(shù)資料
型號(hào)： MFRC50001T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Highly integrated ISO-IEC 14443 A reader IC
封裝： MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,;
文件頁數(shù)： 47/110頁
文件大?。?/td> 841K
代理商： MFRC50001T
MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
47 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
10.5.1.7
InterruptEn register
Control bits to enable and disable passing of interrupt requests.
Table 45.
Bit
Symbol
Access
Table 46.
Bit
7
[1]
This bit can only be set or cleared using bit SetIEn.
10.5.1.8
InterruptRq register
Interrupt request flags.
Table 47.
Bit
Symbol
Access
Table 48.
Bit Symbol
7
SetIRq
InterruptEn register (address: 06h) reset value: 0000 0000b, 00h bit allocation
7
6
5
4
SetIEn
0
TimerIEn
TxIEn
W
R/W
R/W
R/W
3
2
1
0
RxIEn
R/W
IdleIEn
R/W
HiAlertIEn
R/W
LoAlertIEn
R/W
InterruptEn register bit descriptions
Symbol
Value
Description
SetIEn
1
indicates that the marked bits in the InterruptEn register are set
0
clears the marked bits
0
-
reserved
TimerIEn
-
sends the TimerIRq timer interrupt request to pin IRQ
[1]
TxIEn
-
sends the TxIRq transmitter interrupt request to pin IRQ
[1]
RxIEn
-
sends the RxIRq receiver interrupt request to pin IRQ
[1]
IdleIEn
-
sends the IdleIRq idle interrupt request to pin IRQ
[1]
HiAlertIEn
-
sends the HiAlertIRq high alert interrupt request to pin IRQ
[1]
LoAlertIEn -
sends the LoAlertIRq low alert interrupt request to pin IRQ
[1]
6
5
4
3
2
1
0
InterruptRq register (address: 07h) reset value: 0000 0000b, 00h bit allocation
7
6
5
4
SetIRq
0
TimerIRq
TxIRq
W
R/W
D
D
3
2
1
0
RxIRq
D
IdleIRq
D
HiAlertIRq
D
LoAlertIRq
D
InterruptRq register bit descriptions
Value
Description
1
sets the marked bits in the InterruptRq register
0
clears the marked bits in the InterruptRq register
-
reserved
TimerIRq
1
timer decrements the TimerValue register to zero
0
timer decrements are still greater than zero
TxIRq
1
TxIRq is set to logic 1 if one of the following events occurs:
Transceive command; all data transmitted
Authent1 and Authent2 commands; all data transmitted
WriteE2 command; all data is programmed
CalcCRC command; all data is processed
0
when not acted on by Transceive, Authent1, Authent2, WriteE2 or
CalcCRC commands
RxIRq
1
the receiver terminates
0
reception still ongoing
6
5
0
4
3
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