參數(shù)資料
型號： MFRC50001T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Highly integrated ISO-IEC 14443 A reader IC
封裝： MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,;
文件頁數(shù)： 30/110頁
文件大?。?/td> 841K
代理商： MFRC50001T
MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
30 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
9.9.4
Pulse width
The envelope carries the data signal information that is transmitted to the card. It is an
encoded data signal based on the Miller code. In addition, each pause of the Miller
encoded signal is again encoded as a pulse of a fixed width. The width of the pulse is
adjusted using the ModWidth register. The pulse width (t
w
) is calculated using
Equation 9
where the frequency constant (f
clk
) = 13.56 MHz.
(9)
9.10 Receiver circuit
The MFRC500 uses an integrated quadrature demodulation circuit enabling it to extract
the ISO/IEC 14443 A compliant subcarrier from the 13.56 MHz ASK modulated signal
applied to pin RX.
The quadrature demodulator uses two different clocks (Q-clock and I-clock) with a
phase-shift of 90
°
between them. Both resulting subcarrier signals are amplified, filtered
and forwarded to the correlation circuitry. The correlation results are evaluated, digitized
and then passed to the digital circuitry. Various adjustments can be made to obtain
optimum performance for all processing units.
9.10.1
Receiver circuit block diagram
Figure 10
shows the block diagram of the receiver circuit. The receiving process can be
broken down in to several steps. Quadrature demodulation of the 13.56 MHz carrier signal
is performed. To achieve the optimum performance, automatic Q-clock calibration is
recommended (see
Section 9.10.2.1 on page 31
).
The demodulated signal is amplified by an adjustable amplifier. A correlation circuit
calculates the degree of similarity between the expected and the received signal. The
BitPhase register enables correlation interval position alignment with the received signal’s
bit grid. In the evaluation and digitizer circuitry, the valid bits are detected and the digital
results are sent to the FIFO buffer. Several tuning steps are possible for this circuit.
t
w
2ModWidth
1
+
f
clk
=
Fig 10. Receiver circuit block diagram
001aak615
ClkQDelay[4:0]
ClkQCalib
ClkQ180Deg
BitPhase[7:0]
CORRELATION
CIRCUITRY
EVALUATION
AND
DIGITIZER
CIRCUITRY
MinLevel[3:0]
CollLevel[3:0]
RxWait[7:0]
RcvClkSell
s_valid
s_data
s_coll
s_clock
Gain[1:0]
to
TestAnaOutSel
clock
I TO Q
CONVERSION
I-clock
Q-clock
13.56 MHz
DEMODULATOR
RX
VCorrDI
VCorrNI
VCorrDQ
VCorrNQ
VEvalR
VEvalL
VRxFollQ
VRxFollI
VRxAmpI
VRxAmpQ
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