參數(shù)資料
型號(hào): MFRC50001T
廠商: NXP Semiconductors N.V.
元件分類(lèi): 通信及網(wǎng)絡(luò)
英文描述: Highly integrated ISO-IEC 14443 A reader IC
封裝: MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,;
文件頁(yè)數(shù): 55/110頁(yè)
文件大小: 841K
代理商: MFRC50001T
MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
55 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
10.5.4
Page 3: Receiver and decoder control
10.5.4.1
Page register
Selects the page register; see
Section 10.5.1.1 “Page register” on page 43
.
10.5.4.2
RxControl1 register
Controls receiver operation.
Table 77.
Bit
Symbol
Access
Table 78.
Bit
7
6 to 4 111
3 to 2 00
1 to 0 Gain[1:0]
10.5.4.3
DecoderControl register
Controls decoder operation.
Table 79.
Table 80.
Bit
7
6
RxControl1 register (address: 19h) reset value: 0111 0011b, 73h bit allocation
7
6
5
4
0
111
R/W
R/W
3
2
1
0
00
R/W
Gain[1:0]
R/W
RxControl1 register bit descriptions
Symbol
Value
0
0
1
0
Description
these values must not be changed
these values must not be changed
these values must not be changed
defines the receiver’s signal voltage gain factor
20 dB gain factor
24 dB gain factor
31 dB gain factor
35 dB gain factor
00
01
10
11
DecoderControl register (address: 1Ah) reset value: 0000 1000b, 08h bit
allocation
7
6
5
0
RxMultiple ZeroAfterColl
R/W
R/W
R/W
R/W
Bit
Symbol
Access
4
0
3
1
2
1
000
R/W
0
R/W
DecoderControl register bit descriptions
Symbol
Value
0
-
RxMultiple
0
1
ZeroAfterColl
1
Description
this value must not be changed
after receiving one frame, the receiver is deactivated
enables reception of more than one frame
any bits received after a bit-collision are masked to zero. This
helps to resolve the anti-collision procedure as defined in
ISO/IEC 14443 A
this value must not be changed
this value must not be changed
these values must not be changed
5
4
3
2 to 0 000
0
1
0
1
0
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