參數(shù)資料
型號： MFRC50001T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Highly integrated ISO-IEC 14443 A reader IC
封裝： MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,;
文件頁數(shù)： 40/110頁
文件大?。?/td> 841K
代理商： MFRC50001T
MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
40 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
Page 4: RF Timing and channel redundancy
20h
Page
21h
RxWait
22h
ChannelRedundancy
selects the page register
selects the interval after transmission before the receiver starts
selects the method and mode used to check data integrity on
the RF channel
preset LSB value for the CRC register
preset MSB value for the CRC register
do not change these values
selects internal signal applied to pin MFOUT, includes the MSB
of value TimeSlotPeriod; see
Table 101 on page 60
do not change these values
Table 33 on page 43
Table 91 on page 58
Table 93 on page 58
23h
24h
25h
26h
CRCPresetLSB
CRCPresetMSB
PreSet25
MFOUTSelect
Table 95 on page 59
Table 97 on page 59
Table 99 on page 59
Table 101 on page 60
27h
Page 5: FIFO, timer and IRQ pin configuration
28h
Page
29h
FIFOLevel
2Ah
TimerClock
2Bh
TimerControl
2Ch
TimerReload
2Dh
IRQPinConfig
2Eh
PreSet2E
2Fh
PreSet2F
Page 6: reserved registers
30h
Page
31h
reserved
32h
reserved
33h
reserved
34h
reserved
35h
reserved
36h
reserved
37h
reserved
Page 7: Test control
38h
Page
39h
reserved
3Ah
TestAnaSelect
3Bh
reserved
3Ch
reserved
3Dh
TestDigiSelect
3Eh
reserved
3Fh
reserved
PreSet27
Table 103 on page 60
selects the page register
defines the FIFO buffer overflow and underflow warning levels
selects the timer clock divider
selects the timer start and stop conditions
defines the timer preset value
configures pin IRQ output stage
do not change these values
do not change these values
Table 33 on page 43
Table 41 on page 46
Table 107 on page 61
Table 109 on page 62
Table 111 on page 62
Table 113 on page 63
Table 115 on page 63
Table 116 on page 63
selects the page register
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Table 33 on page 43
Table 117 on page 63
selects the page register
reserved
selects analog test mode
reserved
reserved
selects digital test mode
reserved
reserved
Table 33 on page 43
Table 118 on page 64
Table 119 on page 64
Table 121 on page 65
Table 122 on page 65
Table 123 on page 65
Table 125 on page 66
Table 31.
Sub
address
(Hex)
MFRC500 register overview
…continued
Register name
Function
Refer to
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