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| 型號： | MFRC50001T |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Highly integrated ISO-IEC 14443 A reader IC |
| 封裝： | MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,; |
| 文件頁數(shù)： | 70/110頁 |
| 文件大?。?/td> | 841K |
| 代理商： | MFRC50001T |
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MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
70 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
11.2.1.2
RF channel redundancy and framing
Each ISO/IEC 14443 A frame transmitted consists of a Start Of Frame (SOF) pattern,
followed by the data stream and is closed by an End Of Frame (EOF) pattern. These
different phases of the transmission sequence can be monitored using the PrimaryStatus
register ModemState[2:0] bits; see
Section 11.2.4 on page 75
.
Depending on the setting of the ChannelRedundancy register bit TxCRCEn, the CRC is
calculated and appended to the data stream. The CRC is calculated according to the
settings in the ChannelRedundancy register. Parity generation is handled according to the
ChannelRedundancy register ParityEn and ParityOdd bits settings.
11.2.1.3
Transmission of bit oriented frames
The transmitter can be configured to send an incomplete last byte. To achieve this the
BitFraming register’s TxLastBits[2:0] bits must be set at above zero (for example, 1). This
is shown in
Figure 14
.
Figure 14
shows the data stream when bit ParityEn is set in the ChannelRedundancy
register. All fully transmitted bytes are followed by a parity check bit but the incomplete
byte is not followed by a parity check bit. After transmission, the TxLastBits[2:0] bits are
automatically cleared.
Remark:
If the TxLastBits[2:0] bits are not equal to zero, CRC generation must be
disabled. This is done by clearing the ChannelRedundancy register TxCRCEn bit.
11.2.1.4
Transmission of frames with more than 64 bytes
To generate frames of more than 64 bytes, the microprocessor must write data to the
FIFO buffer while the Transmit command is active. The state machine checks the FIFO
buffer status when it starts transmitting the last bit of the data stream; the check time is
shown in
Figure 15
with arrows.
Fig 14. Transmitting bit oriented frames
001aak618
TxLastBits = 0
TxLastBits = 7
TxLastBits = 1
0
7
P
0
7
P
SOF
SOF
SOF
EOF
EOF
EOF
0
7
P
0
6
0
7
P
0
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