參數(shù)資料
型號(hào)： MFRC50001T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Highly integrated ISO-IEC 14443 A reader IC
封裝： MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,;
文件頁數(shù)： 14/110頁
文件大?。?/td> 841K
代理商： MFRC50001T
MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
14 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
Using this format, 12 bytes of EEPROM memory are needed to store a 6-byte key. This is
shown in
Figure 6
.
Example
: The value for the key must be written to the EEPROM.
If the key was: A0h A1h A2h A3h A4h A5h then
5Ah F0h 5Ah E1h 5Ah D2h 5Ah C3h 5Ah B4h 5Ah A5h would be written.
Remark:
It is possible to load data for other key formats into the EEPROM key storage
location. However, it is not possible to validate card authentication with data which will
cause the LoadKeyE2 command (see
Section 11.6.1 on page 81
) to fail.
9.2.3.2
Storage of keys in the EEPROM
The MFRC500 reserves 384 bytes of memory in the EEPROM for the Crypto1 keys. No
memory segmentation is used to mirror the 12-byte structure of key storage. Thus, every
byte of the dedicated memory area can be the start of a key.
Example
: If the key loading cycle starts at the last byte address of an EEPROM block, (for
example, key byte 0 is stored at 12Fh), the next bytes are stored in the next EEPROM
block, for example, key byte 1 is stored at 130h, byte 2 at 131h up to byte 11 at 13Ah.
Based on the 384 bytes of memory and a single key needing 12 bytes, then up to 32
different keys can be stored in the EEPROM.
Remark:
It is not possible to load a key exceeding the EEPROM byte location 1FFh.
9.3 FIFO buffer
An 8
×
64 bit FIFO buffer is used in the MFRC500 to act as a parallel-to-parallel converter.
It buffers both the input and output data streams between the microprocessor and the
internal circuitry of the MFRC500. This makes it possible to manage data streams up to
64 bytes long without needing to take timing constraints into account.
9.3.1
Accessing the FIFO buffer
9.3.1.1
Access rules
The FIFO buffer input and output data bus is connected to the FIFOData register. Writing
to this register stores one byte in the FIFO buffer and increments the FIFO buffer write
pointer. Reading from this register shows the FIFO buffer contents stored at the FIFO
buffer read pointer and increments the FIFO buffer read pointer. The distance between the
write and read pointer can be obtained by reading the FIFOLength register.
Fig 6.
Key storage format
001aak640
0 (LSB)
Master key byte
Master key bits
EEPROM byte
address
Example
k7 k6 k5 k4 k7 k6 k5 k4
n
5Ah
k3 k2 k1 k0 k3 k2 k1 k0
n + 1
F0h
1
k7 k6 k5 k4 k7 k6 k5 k4
n + 2
5Ah
k3 k2 k1 k0 k3 k2 k1 k0
n + 3
E1h
5 (MSB)
k7 k6 k5 k4 k7 k6 k5 k4
n + 10
5Ah
k3 k2 k1 k0 k3 k2 k1 k0
n + 11
A5h
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