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| 型號： | MFRC50001T |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Highly integrated ISO-IEC 14443 A reader IC |
| 封裝： | MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,; |
| 文件頁數(shù)： | 9/110頁 |
| 文件大?。?/td> | 841K |
| 代理商： | MFRC50001T |
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MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
9 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
9.1.3.2
Common read and write strobe
Refer to
Section 13.4.2 on page 87
for timing specification.
9.1.3.3
Common read and write strobe: EPP with handshake
Refer to
Section 13.4.3 on page 88
for timing specification.
Remark:
In the EPP standard a chip select signal is not defined. To cover this situation,
the status of the NCS pin can be used to inhibit the nDStrb signal. If this inhibitor is not
used, it is mandatory that pin NCS is connected to pin DVSS.
Remark:
After each Power-On or Hard reset, the nWait signal on pin A0 is
high-impedance. nWait is defined as the first negative edge applied to the nAStrb pin after
the reset phase. The MFRC500 does not support Read Address Cycle.
Fig 4.
Connection to microprocessor: common read and write strobes
001aak608
address bus (A3 to An)
NCS
A0 to A2
address bus (A0 to A2)
D0 to D7
ALE
data bus (D0 to D7)
HIGH
NRD
Data strobe (NDS)
NWR
Read/Write (R/NW)
DEVICE
ADDRESS
DECODER
non-multiplexed address
NCS
AD0 to AD7
ALE
multiplexed address/data (AD0 to AD7)
Address strobe (AS)
NRD
Data strobe (NDS)
NWR
Read/Write (R/NW)
A2
LOW
A1
HIGH
A0
LOW
DEVICE
ADDRESS
DECODER
Fig 5.
Connection to microprocessor: EPP common read/write strobes and handshake
001aak609
LOW
NCS
AD0 to AD7
ALE
multiplexed address/data (AD1 to AD8)
Address strobe (nAStrb)
NRD
Data strobe (nDStrb)
NWR
Read/Write (nWrite)
A2
HIGH
A1
HIGH
A0
nWait
DEVICE
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