參數(shù)資料
型號： TSB12LV32-EP
英文描述： IC APEX 20KE FPGA 100K 324-FBGA
中文描述： 軍事增強(qiáng)塑料電機(jī)及電子學(xué)工程師聯(lián)合會1394-1995和P1394a兼容通用鏈路層控制器
文件頁數(shù)： 13/106頁
文件大小： 605K
代理商： TSB12LV32-EP
1
–
5
1.5
The terminal functions are described in Table 1
–
1.
Terminal Functions
Table 1
–
1. Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
Microcontroller/Microprocessor Interface
BCLK
6
I
Microinterface clock. Maximum frequency is 60 MHz. In the ColdFire mode,
BCLK is the same as CLK, which is the clock-input signal to the ColdFire.
COLDFIRE
12
I
ColdFire mode. To operate in this mode, COLDFIRE must be asserted high.
LENDIAN
75
I
Little-endian mode for the microinterface. When this terminal is pulled up, the
data on MD0
–
MD15 will be byte-swapped to little endian byte format before it is
written to the CFR or FIFO and after it is read from the CFR or FIFO.
MA0
–
MA6
24
–
21
19
–
17
I
Microcontroller address bus. MA0 is the most significant bit (MSB) of these 7 bits.
M8BIT/SIZ0
13
I
Configuration bit for microinterface. If the microinterface is 8 bits wide, this
terminal must be pulled up to the supply voltage. In ColdFire mode, this terminal
represents burst SIZ0.
MCMODE/SIZ1
14
I
Mode bit for microinterface. If the microinterface wants to communicate in a
handshake manner this terminal must be pulled up to the supply voltage. When
the ColdFire mode terminal (12) is high, this terminal represents burst SIZ1.
MCA
4
O
Microinterface cycle acknowledge. When asserted low, MCA signals an
acknowledge of the microcontroller cycle from the TSB12LV32.
MCS
7
I
Microinterface cycle start. When asserted low, MCS signals the beginning of a
microcontroller operation to the TSB12LV32.
MDINV
11
I
Microinterface data invariant mode. This terminal is meaningful only when
LENDIAN (75) is high. When asserted high, the microinterface operates in the
data invariant mode. When low, the microinterface operates in address invariant
mode.
MD0
–
MD15
99
–
96
94
–
91
89
–
86
84
–
81
I/O
Microinterface bidirectional data bus. MD0 is the most significant bit. However,
byte significance is dependent on the state of the LENDIAN and MDINV
terminals.
MWR
8
I
Microcontroller read/write indicator. When asserted high, MWR indicates a read
access from the TSB12LV32. When asserted low, MWR indicates a write access
to the TSB12LV32.
TEA
3
O
Transfer error acknowledge. This active-low signal is asserted low for one BCLK
cycle whenever there is an illegal transfer request by the microcontroller (i.e.,
requested data transfer size is unsupported or MCS is asserted low for more than
one BCLK cycle in ColdFire mode).
相關(guān)PDF資料
PDF描述
TSB12LV01B-EP FPGA (Field-Programmable Gate Array)
TSB12LV01BPZ FPGA (Field-Programmable Gate Array)
TSB12LV26-EP 672-pin FineLine BGA
TSB12LV22PZP OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
TSB12LV26PZ OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB12LV32I 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 and P1394a Compliant General-Purpose Link-Layer Controller
TSB12LV32IPZ 功能描述:1394 接口集成電路 General-Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV32IPZEP 制造商:Texas Instruments 功能描述:1394 I-TEMP 1394 GENERAL-PURPOSE LINK LAYER CONTROLLER (GP2L - Rail/Tube
TSB12LV32IPZG4 功能描述:1394 接口集成電路 General Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV32PZ 功能描述:1394 接口集成電路 General-Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*