參數(shù)資料
型號: TSB12LV32-EP
英文描述: IC APEX 20KE FPGA 100K 324-FBGA
中文描述: 軍事增強(qiáng)塑料電機(jī)及電子學(xué)工程師聯(lián)合會1394-1995和P1394a兼容通用鏈路層控制器
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文件大?。?/td> 605K
代理商: TSB12LV32-EP
3
10
3.3.2.1
The timing requirements when performing a GRF read access in fixed
timing mode are different from other
access modes. In fixed
timing mode, the GRF must be accessed only on a quadlet boundary. In other
words, only quadlet fetches are legal. If the microinterface is configured for a byte access, this means that
MCSZ must be asserted low for 4 BCLK cycles, as shown in Figure 3
11. If configured for word access, then
MCSZ must only be asserted for 2 BCLK cycles, as shown in Figure 3
12.
GRF READ
BCLK
COLDFIRE
M8BIT/SIZ0
MCMODE/SIZ1
MWR
MCS
MCA
MA[0:6]
MD[0:7]
MD[8:15]
XX
XX
ZZ
XX
ZZ
ZZ
ZZ
GRF ADDRESS
D1
D2
D3
D4
Figure 3
11. GRF Read Access (Byte Fixed-Timing Mode)
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