參數(shù)資料
型號: TSB12LV32-EP
英文描述: IC APEX 20KE FPGA 100K 324-FBGA
中文描述: 軍事增強(qiáng)塑料電機(jī)及電子學(xué)工程師聯(lián)合會1394-1995和P1394a兼容通用鏈路層控制器
文件頁數(shù): 45/106頁
文件大?。?/td> 605K
代理商: TSB12LV32-EP
3
8
BCLK
COLDFIRE
M8BIT/SIZ0
MCMODE/SIZ1
MWR
MCS
MCA
MA[0:6]
MD[0:7]
MD[8:15]
A1
A2
D2
D4
D6
D8
D10
D1
D3
D5
D7
D9
Figure 3
8. Word Fixed-Timing Read
Byte fixed timing write and word fixed timing write are shown in Figure 3
9 and Figure 3
10.
The first data transfer takes one extra wait cycle. All subsequent data transfers take only one BCLK cycle.
For an 8-bit data bus, MD[0:7] is not used (don
t care) and is driven with zeros. If the write transaction is
accessing the CFR register, it may not cross any register boundary. First write data for each ATF quadlet
must start at byte0. Write accesses to the ATF must be quadlet aligned. The micro interface will wait for all
bytes of each quadlet to be available before creating a write request to the ATF. If a transfer error condition
occurs, TEA will be asserted low for one BCLK cycle. An error condition can occur if the MCMODE/SIZ1
or M8BIT/SIZ0 lines transition during the access cycle.
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