參數(shù)資料
型號(hào): TSB12LV32-EP
英文描述: IC APEX 20KE FPGA 100K 324-FBGA
中文描述: 軍事增強(qiáng)塑料電機(jī)及電子學(xué)工程師聯(lián)合會(huì)1394-1995和P1394a兼容通用鏈路層控制器
文件頁(yè)數(shù): 56/106頁(yè)
文件大?。?/td> 605K
代理商: TSB12LV32-EP
4
3
Table 4
1. Receiver Routing
AR0
0
AR1
0
DMASYNC
X
DMRX
0
DATA MOVER (DM)
Receives no data;
Power-on default
GENERAL-RECEIVE FIFO (GRF)
Receives all data (asynchronous and
isochronous); power-on default
1
1
Receives Read Response
Packets with a tlabel of 11XXXX
Receives all other asynchronous
packets and isochronous packets
0
1
1
1
Receives asynchronous data
only
Receives isochronous/asynchronous
streaming data only
X
0
Receives no data
Receives all data
0
1
Receives isochronous/
asynchronous streaming data
only
Receives asynchronous data
1
0
X
0
Receives no data
Receives all data
0
1
Receive no data
Receives all data
1
1
Receives addressed write
request asynchronous packets in
the address range of
0000_0000_0000 -
0000_FFFF_FFFFh
Receives addressed asynchronous
packets in the address range of
0001_0000_0000-FFFF_FFFF_FFFFh.
Also receives any asynchronous
packets not going to the DM port
regardless of the address. Receives
isochronous packets too.
1
1
X
0
Receives no data
Receives all data
X
1
Receive all data (asynchronous
and isochronous)
Receives no data
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