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參數(shù)資料
| 型號： | TSB12LV32-EP |
| 英文描述： | IC APEX 20KE FPGA 100K 324-FBGA |
| 中文描述： | 軍事增強塑料電機及電子學(xué)工程師聯(lián)合會1394-1995和P1394a兼容通用鏈路層控制器 |
| 文件頁數(shù)： | 41/106頁 |
| 文件大?。?/td> | 605K |
| 代理商： | TSB12LV32-EP |
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3
–
4
3.3
The micro interface can be configured to operate in one of the following modes: handshake, fixed-timing,
or ColdFire mode. Burst transfers are only supported in the latter two modes.
3.3.1
Microcontroller Handshake Mode
Byte handshake read and word handshake read are shown in Figure 3
–
3 and Figure 3
–
4, respectively.
Microcontroller Interface Read/Write Timing
The MCS, MCA handshake timing sequence for a read transaction can be summarized as follows:
1.
The host takes MCS low to signal the start of access. When the rising edge of BCLK samples
MCS low and MWR high, the MD[0:15] lines are enabled and driven with the read value. For an
8-bit data bus, MD[0:7] lines are not used.
2.
Following the next rising edge of BCLK, the TSB12LV32 takes MCA low to signal that the
requested operation is complete. This is ensured to take place after two BCLK cycles. MCA
remains low with the MD lines containing valid read data until the micro interface releases MCS
(high state)
3.
The host takes MCS high to signal the end of the process.
4.
The TSB12LV32 takes MCA high to acknowledge the end of the access. This 3-states the MD
lines.
Another read or write transaction can begin after the next rising edge of BCLK. Note that data size is
determined by the MCMODE/SIZ1 and M8BIT/SIZ0 signals. The ColdFire signal is only asserted high when
the micro interface is operating in ColdFire mode.
BCLK
COLDFIRE
M8BIT/SIZ0
MCMODE/SIZ1
MWR
MCS
MCA
MCADR[0:6]
MD[0:7]
MD[8:15]
A1
D1
D2
A2
Figure 3
–
3. Byte Handshake Read
Figure 3
–
4 shows a word handshake read transaction. In this case, all 16 bits of the MD lines are used. Note
that MD[0] contains the MSB and MD[15] contains the LSB. As in the byte read case, another read or write
transaction can begin after the next rising edge of BCLK.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV32I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 and P1394a Compliant General-Purpose Link-Layer Controller |
| TSB12LV32IPZ | 功能描述:1394 接口集成電路 General-Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV32IPZEP | 制造商:Texas Instruments 功能描述:1394 I-TEMP 1394 GENERAL-PURPOSE LINK LAYER CONTROLLER (GP2L - Rail/Tube |
| TSB12LV32IPZG4 | 功能描述:1394 接口集成電路 General Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV32PZ | 功能描述:1394 接口集成電路 General-Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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