參數(shù)資料
型號: TSB12LV32-EP
英文描述: IC APEX 20KE FPGA 100K 324-FBGA
中文描述: 軍事增強塑料電機及電子學(xué)工程師聯(lián)合會1394-1995和P1394a兼容通用鏈路層控制器
文件頁數(shù): 73/106頁
文件大小: 605K
代理商: TSB12LV32-EP
5
17
Figure 5
27 and Figure 5
28 show the timing diagram for this mode for the quadlet receive and the block
receive cases, respectively. For simplicity, a data block size of three quadlets was selected in Figure 5
28
DMCLK
DMRW
DMD[0:15]
PKTFLAG
DMDONE
Figure 5
27. Asynchronous Quadlet Receive Without Headers and Trailer at 400 Mbps
DMCLK
DMRW
DMD[0:15]
PKTFLAG
DMDONE
Figure 5
28. Asynchronous Block Receive Without Headers and Trailer at 400 Mbps
5.3
In this mode the DMD lines are only 1 byte wide => the maximum speed is only 200 Mbit/sec. Only bits 0
7
will be used for the data bus. DMERROR will be asserted if transmission of a 400 Mbit/sec packet is
attempted.
Data Mover Byte Mode
5.4
In this mode the DMD[0:15] bytes are swapped. If the data mover is in byte mode, the least significant byte
is fetched first (Figure 5
29). If the data mover is not in byte mode, the least significant word is fetched first
and the byte order is then swapped (Figure 5
30).
Data Mover Endian Swapping
DMCLK
DMRW
DMD[0:15]
NORM_LINK_DATA
SWAP_LINK_DATA
01020304
A1B2C3D4
04030201
D4C3B2A1
01
02
03
04
A1
B2
C3
D4
Figure 5
29. Endian Swapping in Byte Mode
DMCLK
DMRW
DMD[0:15]
NORM_LINK_DATA
SWAP_LINK_DATA
01020304
A1B2C3D4
04030201
D4C3B2A1
0102
0304
A1B2
C3D4
Figure 5
30. Endian Swapping in Word Mode
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