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| 型號： | TSB12LV32-EP |
| 英文描述： | IC APEX 20KE FPGA 100K 324-FBGA |
| 中文描述： | 軍事增強(qiáng)塑料電機(jī)及電子學(xué)工程師聯(lián)合會1394-1995和P1394a兼容通用鏈路層控制器 |
| 文件頁數(shù)： | 85/106頁 |
| 文件大小： | 605K |
| 代理商： | TSB12LV32-EP |
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7
–
7
7.2
The format of the isochronous-transmit packet is shown in Figure 7
–
8 and is described in Table 7
–
5. The
data for each channel must be presented to the isochronous-transmit FIFO interface in this format in the
order that packets are to be sent. The transmitter sends any packets available at the isochronous-transmit
interface immediately following reception or transmission of the cycle-start message. The speed at which
the current packet is sent is determined by the
speed
field in the DM control register (bits 22-23)
Isochronous Transmit (Host Bus to TSB12LV32)
3
2
1
0
7
6
5
4
11
10
9
8
15
14
13
12
19
18
17
16
20 21
31
30
29
28
27
26
25
24
23
22
isochronous data
0
1
sy
tCode
TAG
dataLength
chanNum
1
0
Figure 7
–
8. Isochronous-Transmit Format
Table 7
–
5. Isochronous-Transmit Functions
FIELD NAME
DESCRIPTION
dataLength
The dataLength field indicates the number of bytes in the current packet
TAG
The TAG field indicates the format of data carried by the isochronous packet (00 = formatted,
01
–
11 are reserved).
chanNum
The chanNum field carries the channel number with which the current data is associated.
tCode
The transaction code for the current packet (tCode=Ah).
sy
The sy field carries the transaction layer-specific synchronization bits.
isochronous data
The isochronous data field contains the data to be sent with the current packet. The first byte of
data must appear in byte 0 of the first quadlet of this field. If the last quadlet does not contain four
bytes of data, the unused bytes should be padded with zeros.
7.2.1
The format of the iscohronous-receive data through the DM is shown in Figure 7
–
8 and is described in
Table 7
–
6. The data length, which is found in the header of the packet, determines the number of bytes in
an isochronous packet. For iscohronous-receive through the FIFO, the last quadlet will be inserted as the
first quadlet in the receive data, as shown in Figure 7
–
9.
Isochronous Receive (TSB12LV32 to Host Bus)
3
2
1
0
7
6
5
4
11
10
9
8
15
14
13
12
19
18
17
16
20 21
31
30
29
28
27
26
25
24
23
22
isochronous data
0
1
sy
tCode
TAG
dataLength
chanNum
1
0
spd
numofQuadlets
0
0
0
0
0
errCode
0
0
0
0
0
0
Figure 7
–
9. Data Mover Isochronous-Receive Format
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV32I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 and P1394a Compliant General-Purpose Link-Layer Controller |
| TSB12LV32IPZ | 功能描述:1394 接口集成電路 General-Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV32IPZEP | 制造商:Texas Instruments 功能描述:1394 I-TEMP 1394 GENERAL-PURPOSE LINK LAYER CONTROLLER (GP2L - Rail/Tube |
| TSB12LV32IPZG4 | 功能描述:1394 接口集成電路 General Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV32PZ | 功能描述:1394 接口集成電路 General-Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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