- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365967 > TSB12LV32-EP IC APEX 20KE FPGA 100K 324-FBGA PDF資料下載
參數(shù)資料
| 型號： | TSB12LV32-EP |
| 英文描述： | IC APEX 20KE FPGA 100K 324-FBGA |
| 中文描述： | 軍事增強(qiáng)塑料電機(jī)及電子學(xué)工程師聯(lián)合會1394-1995和P1394a兼容通用鏈路層控制器 |
| 文件頁數(shù)： | 99/106頁 |
| 文件大?。?/td> | 605K |
| 代理商： | TSB12LV32-EP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁當(dāng)前第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁
8
–
6
address. All status transfers are either 4 or 16 bits unless interrupted by a received packet. The status flags
are considered to have been successfully transmitted to the TSB12LV32 immediately upon being sent, even
if a received packet subsequently interrupts the status transfer. Register contents are considered to have
been successfully transmitted only when all 8 bits of the register have been sent. A status transfer is retried
after being interrupted only if any status flags remain to be sent, or if a register transfer has not yet completed.
The definition of the bits in the status transfer are shown in Table 8
–
9 and the timing is shown in Figure 8
–
3.
Table 8
–
10. Status Bits
BIT(S)
NAME
DESCRIPTION
0
Arbitration Reset Gap
Indicates that the Phy has detected that the bus has been idle for an arbitration
reset gap time (as defined in IEEE Std 1394
–
1995). This bit is used by the
TSB12LV32 in the busy/retry state machine.
1
Subaction Gap
Indicates that the Phy has detected that the bus has been idle for a subaction gap
time (as defined in IEEE Std 1394
–
1995). This bit is used by the TSB12LV32 to
detect the completion of an isochronous cycle.
2
Bus Reset
Indicates that the Phy has entered the bus reset start state.
3
Interrupt
Indicates that a Phy interrupt event has occurred. An interrupt event may be a
configuration time-out, cable-power voltage falling too low, a state time-out, or a
port status change.
4
–
7
Address
This field holds the address of the Phy register whose contents are being
transferred to the TSB12LV32.
8
–
15
Data
This field holds the register contents.
00
00
(a)
01
(b)
00
00
S[14:15]
S[0:1]
D0, D1
CTL0, CTL1
SYSCLK
Figure 8
–
3. Status Transfer Timing
The sequence of events for a status transfer is as follows:
Status transfer initiated. The Phy indicates a status transfer by asserting status on the CTL lines
along with the status data on the D0 and D1 lines (only 2 bits of status are transferred per cycle).
Normally (unless interrupted by a receive operation), a status transfer will be either 2 or 8 cycles
long. A 2-cycle (4-bit) transfer occurs when only status information is to be sent. An 8-cycle
(16-bit) transfer occurs when register data is to be sent in addition to any status information.
Status transfer terminated. The Phy normally terminates a status transfer by asserting idle on the
CTL lines. The Phy may also interrupt a status transfer at any cycle by asserting receive on the
CTL lines to begin a receive operation. The Phy shall assert at least one cycle of idle between
consecutive status transfers.
8.4
Whenever the Phy detects the data-prefix state on the serial bus, it initiates a receive operation by asserting
Receive on the CTL terminals and a logic 1 on each of the D terminals (data-on indication). The Phy indicates
the start of a packet by placing the speed code (encoded as shown in Table 8
–
11 on the D terminals, followed
by packet data. The Phy holds the CTL terminals in the receive state until the last symbol of the packet has
Receive Operation
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB12LV01B-EP | FPGA (Field-Programmable Gate Array) |
| TSB12LV01BPZ | FPGA (Field-Programmable Gate Array) |
| TSB12LV26-EP | 672-pin FineLine BGA |
| TSB12LV22PZP | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB12LV26PZ | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV32I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 and P1394a Compliant General-Purpose Link-Layer Controller |
| TSB12LV32IPZ | 功能描述:1394 接口集成電路 General-Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV32IPZEP | 制造商:Texas Instruments 功能描述:1394 I-TEMP 1394 GENERAL-PURPOSE LINK LAYER CONTROLLER (GP2L - Rail/Tube |
| TSB12LV32IPZG4 | 功能描述:1394 接口集成電路 General Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV32PZ | 功能描述:1394 接口集成電路 General-Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。