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參數(shù)資料
| 型號： | TSB12LV32-EP |
| 英文描述： | IC APEX 20KE FPGA 100K 324-FBGA |
| 中文描述： | 軍事增強(qiáng)塑料電機(jī)及電子學(xué)工程師聯(lián)合會1394-1995和P1394a兼容通用鏈路層控制器 |
| 文件頁數(shù)： | 30/106頁 |
| 文件大?。?/td> | 605K |
| 代理商： | TSB12LV32-EP |
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2
–
14
2.2.8
Diagnostic Register at 20h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
29 30 31
28
B
B
B
B
B
B
R
R
B
B
STATESEL0
STATESEL1
STATESEL2
The power-up reset value of this register =
0000_4AD0
’
h
BIT
NUMBER
BIT NAME
FUNCTION
DIR
DESCRIPTION
0
B0_BUSY
Byte 0 busy
R
Byte 0 busy. When this bit is set, no microinterface write to byte 0 of
any CFRs is allowed. The microinterface must first poll this bit
before writing to byte 0.
1
B1_BUSY
Byte 1 busy
R
Byte 1 busy. When this bit is set, no microinterface write to byte 1 of
any CFRs is allowed. The microinterface must first poll this bit
before writing to byte 1.
2
B2_BUSY
Byte 2 busy
R
Byte 2 busy. When this bit is set, no microinterface write to byte 2 of
any CFRs is allowed. The microinterface must first poll this bit
before writing to byte 2.
3
B3_BUSY
Byte 3 busy
R
Byte 3 busy. When this bit is set, no microinterface write to byte 3 of
any CFRs is allowed. The microinterface must first poll this bit
before writing to byte 3.
4
B0_PND
Byte 0
pending
R
Byte 0 pending. When this bit is set, it indicates that byte 0 of a word
or quadlet write has been accepted and the hardware is waiting for
the remaining bytes to be written. When the full write is complete,
this bit will be cleared.
5
B1_PND
Byte 1
pending
R
Byte 1 pending. When this bit is set, it indicates that byte 1 of a word
or quadlet write has been accepted and the hardware is waiting for
the remaining bytes to be written. When the full write is complete,
this bit will be cleared.
6
B2_PND
Byte 2
pending
R
Byte 2 pending. When this bit is set, it indicates that byte 2 of a word
or quadlet write has been accepted and the hardware is waiting for
the remaining bytes to be written. When the full write is complete,
this bit will be cleared.
7
B3_PND
Byte 3
pending
R
Byte 3 pending. When this bit is set, it indicates that byte 3 of a word
or quadlet write has been accepted and the hardware is waiting for
the remaining bytes to be written. When the full write is complete
this bit will be cleared.
8
RAM_TEST
R/W
This bit can be set only when TESTMODE is high. When this bit is
set, the built in self test(BIST) for the FIFOs (transmit and receive)
will be run. On completion of the test hardware will reset this bit to 0
and simultaneously set bit 30 and 31.
9
REGRW
Register
read/write
access
R/W
When REGRW is set, write-protected bits in various registers can
be written to.
10
–
15
RESERVED
Reserved
16
–
19
STATSEL0
State0
select
R/W
Status output select bits. Used to program the output of STAT0
terminal. See table in
Operation
section.
20
–
23
STATSEL1
State1
select
R/W
Status output select bits. Used to program the output of STAT1
terminal. See table in
Operation
section.
24
–
27
STATSEL2
State2
select
R/W
Status output select bits. Used to program the output of STAT2
terminal. See table in Operation section.
28
–
31
RESERVED
Reserved
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV32I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 and P1394a Compliant General-Purpose Link-Layer Controller |
| TSB12LV32IPZ | 功能描述:1394 接口集成電路 General-Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV32IPZEP | 制造商:Texas Instruments 功能描述:1394 I-TEMP 1394 GENERAL-PURPOSE LINK LAYER CONTROLLER (GP2L - Rail/Tube |
| TSB12LV32IPZG4 | 功能描述:1394 接口集成電路 General Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV32PZ | 功能描述:1394 接口集成電路 General-Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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