參數(shù)資料
型號: TSB12LV32-EP
英文描述: IC APEX 20KE FPGA 100K 324-FBGA
中文描述: 軍事增強塑料電機及電子學工程師聯(lián)合會1394-1995和P1394a兼容通用鏈路層控制器
文件頁數(shù): 82/106頁
文件大?。?/td> 605K
代理商: TSB12LV32-EP
7
4
3
2
1
0
7
6
5
4
11
10
9
8
15
14
13
12
19
18
17
16
20 21
31
30
29
28
27
26
25
24
23
22
spd
numofQuadlets
sourceID
destinationOffsetHigh
0
0
0
0
0
ackCode
0
0
0
0
0
0
prioity
tCode
rt
tLabel
destinationID
destinationOffsetLow
quadlet data (for write request and read response)
Figure 7
4. FIFO Quadlet-Receive Format
The quadlet-receive format through the DM is shown in Figure 7
5 and is described in Table 7
3. This format
is similar to the quadlet receive format for the TSB12LV31(GPLynx). The first 16 bits of the first quadlet
contain the destination node and bus ID, and the remaining 16 bits contain packet-control information. The
first 16 bits of the second quadlet contain the node and bus ID of the source, and the remaining 16 bits of
the second and third quadlets contain the 48-bit, quadlet-aligned destination offset address. The fourth
quadlet contains data that is used by write requests and read responses. For read requests and write
responses, the quadlet data field is omitted. The last quadlet (trailer) contains the packet-reception status
that is added by the TSB12LV32.
3
2
1
0
7
6
5
4
11
10
9
8
15
14
13
12
19
18
17
16
20 21
31
30
29
28
27
26
25
24
23
22
spd
numofQuadlets
sourceID
destinationOffsetHigh
0
0
0
0
0
ackCode
0
0
0
0
0
0
prioity
tCode
rt
tLabel
destinationID
destinationOffsetLow
quadlet data (for write request and read response)
Figure 7
5. Data Mover Quadlet-Receive Format
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相關代理商/技術參數(shù)
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