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參數(shù)資料
| 型號： | TSB12LV32-EP |
| 英文描述： | IC APEX 20KE FPGA 100K 324-FBGA |
| 中文描述： | 軍事增強塑料電機及電子學工程師聯(lián)合會1394-1995和P1394a兼容通用鏈路層控制器 |
| 文件頁數(shù)： | 81/106頁 |
| 文件大?。?/td> | 605K |
| 代理商： | TSB12LV32-EP |
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7
–
3
3
2
1
0
7
6
5
4
11
10
9
8
15
14
13
12
19
18
17
16
20 21
31
30
29
28
27
26
25
24
23
22
prioity
tCode
rt
tLabel
spd
destinationID
dataLength
destinationOffsetHigh
destinationOffsetLow
block data
extended_tCode
Figure 7
–
3. Block-Transmit Format
Table 7
–
2. Block-Transmit Format Functions
FIELD NAME
DESCRIPTION
Spd
The spd field indicates the speed at which the current packet is to be sent. 00 = 100 Mb/s,
01 = 200 Mb/s, and 10 = 400 Mb/s, and 11 is undefined for this implementation.
TLabel
The tLabel field is the transaction label, which is a unique tag for each outstanding transaction
between two nodes. This field is used to pair up a response packet with its corresponding
request packet.
Rt
The rt field is the retry code for the current packet is 00 = new, 01 = retry_X, 10 = retryA, and
11 = retryB.
TCode
tCode is the transaction code for the current packet (see Table 6
–
10 of IEEE
–
1394 standard).
priority
The priority level for the current packet. For cable implementation, the value of the bits must
be zero. For backplane implementation, see clause 5.4.1.3 and 5.4.2.1 of the IEEE
–
1394
standard.
destinationID
The destinationID field is the concatenation of the 10-bit bus number and the 6-bit node
number that forms the node address to which the current packet is being sent.
destination OffsetHigh,
destination OffsetLow
The concatenation of the destination OffsetHigh and the destination OffsetLow fields
addresses a quadlet in the destination node address space. This address must be quadlet
aligned (modulo 4). The upper 4 bits of the destination OffsetHigh field are used as the
response code for lock-response packets and the remaining bits are reserved.
dataLength
The dataLength filed contains the number of bytes of data to be transmitted in the packet.
extended_tCode
The block extended_tCode to be performed on the data in the current packet (see Table 6
–
11
of the IEEE
–
1394 standard).
block data
The block data field contains the data to be sent. If dataLength is 0, no data should be written
into the FIFO for this field. Regardless of the destination or source alignment of the data, the
first byte of the block must appear in byte 0 of the first quadlet.
7.1.3
Quadlet Receive
The quadlet-receive format through the FIFO is shown in Figure 7
–
4 and is described in Table 7
–
3. The first
quadlet (trailer) contains the packet-reception status that is added by the TSB12LV32. The first 16 bits of
the second quadlet contain the destination node and bus ID, and the remaining 16 bits contain
packet-control information. The first 16 bits of the third quadlet contain the node and bus ID of the source,
and the remaining 16 bits of the third quadlet and the fourth quadlet contain the 48-bit, quadlet-aligned
destination offset address. The last quadlet contains data that is used by write requests and read responses.
For read requests and write responses, the quadlet data field is omitted.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV32I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 and P1394a Compliant General-Purpose Link-Layer Controller |
| TSB12LV32IPZ | 功能描述:1394 接口集成電路 General-Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV32IPZEP | 制造商:Texas Instruments 功能描述:1394 I-TEMP 1394 GENERAL-PURPOSE LINK LAYER CONTROLLER (GP2L - Rail/Tube |
| TSB12LV32IPZG4 | 功能描述:1394 接口集成電路 General Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV32PZ | 功能描述:1394 接口集成電路 General-Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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