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| 型號(hào)： | TSB12LV32-EP |
| 英文描述： | IC APEX 20KE FPGA 100K 324-FBGA |
| 中文描述： | 軍事增強(qiáng)塑料電機(jī)及電子學(xué)工程師聯(lián)合會(huì)1394-1995和P1394a兼容通用鏈路層控制器 |
| 文件頁數(shù)： | 68/106頁 |
| 文件大?。?/td> | 605K |
| 代理商： | TSB12LV32-EP |
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5
–
12
DMCLK
DMRW
DMD[0:15]
DMREADY
DMPRE
DMDONE
Figure 5
–
15. Isochronous Transmit With Auto Header Insertion at 100 Mbps
5.2.2
Upon receiving a high on DMREADY, the following sequence of operations is performed:
Isochronous Transmit Without Automatic Header Insertion
Step 1:
DMDONE will be asserted low (deactivated) at the next DMCLK cycle.
Step 2:
DMPRE will pulse for one DMCLK cycle before the first header quadlet is sent.
Step 3:
The data mover will fetch the header by asserting DMRW high.
Step 4:
The data mover will then load the header into the header0 register and request the data
to be transmitted out on the 1394 bus by the link core.
Step 5:
The link will fetch the header.
Step 6:
DMPRE will pulse for one DMCLK cycle before the first data quadlet is sent.
Step 7:
The data mover will then begin to fetch the data payload by asserting DMRW high.
Step 8:
When the last data quadlet has been fetched by the link, the data mover will check if the
number of channels specified by the control registers have been sent. If all channels have
been sent the data mover will wait for a subaction gap to occur before asserting DMDONE
high to indicate the end of the cycle. Otherwise the DM will fetch the next header and load
it into the next header register and then begin fetching the data payload until all channels
are complete.
Figure 5
–
16 shows the timing diagram for this mode at a data transmit rate of 400 Mbps. The dashed
sections indicate repetitive behaviour (when the payload is more than two quadlets long).
DMCLK
DMRW
DMD[0:15]
DMREADY
DMPRE
DMDONE
Figure 5
–
16. Isochronous Transmit Without Auto Header Insertion
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| TSB12LV01BPZ | FPGA (Field-Programmable Gate Array) |
| TSB12LV26-EP | 672-pin FineLine BGA |
| TSB12LV22PZP | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV32I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 and P1394a Compliant General-Purpose Link-Layer Controller |
| TSB12LV32IPZ | 功能描述:1394 接口集成電路 General-Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV32IPZEP | 制造商:Texas Instruments 功能描述:1394 I-TEMP 1394 GENERAL-PURPOSE LINK LAYER CONTROLLER (GP2L - Rail/Tube |
| TSB12LV32IPZG4 | 功能描述:1394 接口集成電路 General Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV32PZ | 功能描述:1394 接口集成電路 General-Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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