參數(shù)資料
型號: μPDPD30101
廠商: NEC Corp.
英文描述: 64-Bit Micro[rocessor(64位微處理器)
中文描述: 64位微[rocessor(64位微處理器)
文件頁數(shù): 15/97頁
文件大小: 409K
代理商: ΜPDPD30101
μ
PD30101
14
2. INTERNAL BLOCKS
2.1 V
R
4100 CPU Core
(1) CPU
The CPU processes integer instructions and consists of 64-bit register files, a 64-bit integer data bus, and
a sum-of-products operation unit.
(2) Coprocessor 0 (CP0)
The CP0 has a memory management unit (MMU) and an exception processing function. The MMU translates
addresses and checks whether an access is made between different types (user, supervisor, or kernel) of
memory segments. Virtual addresses are translated to physical addresses by TLB (high-speed translation
lookaside buffer).
(3) Instruction cache
The instruction cache is of direct mapping, virtual index, and physical tag type.
(4) Data cache
The data cache is of direct mapping, virtual index, physical tag, and write back type.
(5) CPU bus interface
The CPU bus interface controls data transfer between the V
R
4100 CPU core and BCU, one of the peripheral
units. As the bus interface for the V
R
4100 CPU core, two 32-bit address/data multiplexed buses each for
input and output, clock signals, and interrupt control signals are used.
(6) Clock generator
A 32.768-kHz crystal oscillator is oscillated by an internal oscillation circuit and multiplied by 1012 by PLL
(phase-locked loop) to generate a pipeline clock (PClock). The system interface clock (SClock) is generated
from PClock.
2.2 BCU (Bus Control Unit)
The BCU internally transfers data with the V
R
4100 CPU core via SysAD bus. It also controls the LCD controller,
DRAM, ROM (flash memory or mask ROM), and PCMCIA controller connected to the system bus, and transfers data
with the above devices via ADD and DATA buses.
2.3 RTC (Real-time Clock)
The RTC has a precise counter that operates with a 32.768-kHz clock supplied from the clock generator. It also has
several counters and compare registers for various interrupts.
2.4 DSU (Deadman’s Switch Unit)
The DSU is used to check whether the processor is operating normally. If the software does not clear the register of
this unit at specific intervals, the system is shut down.
2.5 ICU (Interrupt Control Unit)
The ICU controls interrupt requests generated from the external and internal sources of the V
R
4101, and reports an
interrupt request, if any, to the V
R
4100 CPU core.
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