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參數(shù)資料
| 型號： | μPDPD30101 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-Bit Micro[rocessor(64位微處理器) |
| 中文描述： | 64位微[rocessor（64位微處理器） |
| 文件頁數(shù)： | 31/97頁 |
| 文件大?。?/td> | 409K |
| 代理商： | ΜPDPD30101 |
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μ
PD30101
30
Table 3-2. Types of Exceptions
Exception
Symbol
Description
Cold reset
—
This exception occurs if the ColdReset (internal) and Reset (internal) signals
are simultaneously asserted active (for details, refer to
Figures 4-1
through
4-5
). As a result, the instruction execution is stopped, and the handler on the
reset vector is executed. The internal status, except some bits of the status
registers, is undefined.
Soft reset
—
This exception occurs if the Reset (internal) signal is asserted active. As a
result, the instruction execution is stopped, and the handler on the reset vector
is executed. The internal status before soft reset is retained. However, the
current V
R
4101 does not support soft reset.
NIMI
—
This exception occurs if the NMI (internal) signal is asserted active.
TLB non-coincidence
TLBL/TLBS
This exception occurs if there is no TLB entry that coincides with an address
to be referenced in the 32-bit mode.
Extended addressing
TLB non-coincidence
TLBL/TLBS
This exception occurs if there is no TLB entry that coincides with an address
to be referenced in the 64-bit mode.
TLB invalid
TLBL/TLBS
This exception occurs if the TLB entry that coincides with the virtual address
to be referenced is invalid (V bit = 0).
TLB modify
Mod
This exception occurs if the TLB entry that coincides with the virtual address
to be referenced is valid but is disabled from being written (D bit = 0) when the
store instruction is executed.
Bus error
IBE/DBE
This exception occurs when the external agent indicates an error of data on the
SysCmd bus by using an external interrupt to the bus interface (bus time-out,
bus parity error, or invalid physical memory address or access type).
Address error
AdEL/AdES
This exception occurs if an attempt is made to execute the LH, SH/LW/SW, LD,
or SD instruction to the half word/word/double word not located at the half word/
word/double word boundary, or if an attempt is made to reference the virtual
address that cannot be accessed.
Integer overflow
Ov
This exception occurs if a 2’s complement overflow occurs as a result of addition
or subtraction.
Trap
Tr
This exception occurs if the condition is true as a result of executing the trap
instruction.
System call
Sys
This exception occurs if the SYSCALL instruction is executed.
Breakpoint
Bp
This exception occurs if the BREAK instruction is executed.
Reserved instruction
RI
This exception occurs if an instruction with an undefined op code (bits 31-26)
or SPECIAL instruction with an undefined op code (bits 5-0) is executed.
Coprocessor non-usable
CpU
This exception occurs if the coprocessor instruction is executed when the
corresponding coprocessor enable bit is not set.
Interrupt
Int
This exception occurs if one of the eight interrupt sources becomes active.
Cache error
—
This exception occurs if a parity error is detected in the internal cache or system
interface.
Watch
WATCH
This exception occurs if an attempt is made to reference a physical address set
by the watch Lo/Hi register with the load/store instruction.
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