參數(shù)資料
型號： μPDPD30101
廠商： NEC Corp.
英文描述： 64-Bit Micro[rocessor(64位微處理器)
中文描述： 64位微[rocessor（64位微處理器）
文件頁數(shù)： 27/97頁
文件大小： 409K
代理商： ΜPDPD30101
μ
PD30101
26
Figure 3-10. Details of xkphys Area
Address error
4G bytes
w/o TLB mapping
cacheable
Address error
4G bytes
w/o TLB mapping
cacheable
Address error
4G bytes
w/o TLB mapping
cacheable
Address error
Address error
Address error
4G bytes
w/o TLB mapping
Uncacheable
Address error
4G bytes
w/o TLB mapping
Uncacheable
Address error
4G bytes
w/o TLB mapping
Uncacheable
F
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8
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0 x
4G bytes
w/o TLB mapping
cacheable
4G bytes
w/o TLB mapping
cacheable
3.6.2 Address translation
Virtual addresses are translated into physical addresses by the internal TLB (Translation Lookaside Buffer) in page
units. The TLB has a full-associative configuration and has 64 entries at the virtual address side and 32 entries at the
physical address side. The page size is variable from 1K to 256K byte.
If a TLB entry is not found, a TLB non-coincidence exception occurs in the 32-bit mode, and an XTLB non-coincidence
exception occurs in the 64-bit mode. Change the contents of the TLB in software.
The following figure outlines address translation.
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