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參數(shù)資料
| 型號： | μPDPD30101 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-Bit Micro[rocessor(64位微處理器) |
| 中文描述： | 64位微[rocessor（64位微處理器） |
| 文件頁數(shù)： | 40/97頁 |
| 文件大小： | 409K |
| 代理商： | ΜPDPD30101 |
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μ
PD30101
39
is almost 0 W (not completely 0 W because a 32.768-kHz oscillator and internal circuits that operate at 32.768
kHz exist).
4.4.2 Privilege mode
The V
R
4101 supports three system modes: kernel-, supervisor-, and user-extended addressing. These three modes
are explained below.
(1) Kernel-extended addressing mode
When the KX bit of the status register is set, extended TLB non-coincidence exception vector is used for
TLB non-coincidence of the kernel address. In the kernel mode, the MIPS III op code can be always used,
regardless of the KX bit.
(2) Supervisor-extended addressing mode
When the SX bit of the status register is set, the MIPS III op code can be used in the supervisor mode, and
extended TLB non-coincidence exception vector is used for TLB non-coincidence of the supervisor address.
(3) User-extended addressing mode
When the UX bit of the status bit is set, the MIPS III op code can be used in the user mode, and the extended
TLB non-coincidence exception vector is used for TLB non-coincidence of the user address. When this bit
is cleared, the MIPS I and II op codes and 32-bit virtual addresses are used.
4.4.3 Reverse endian
When the RE bit of the status register is set, the endian is reversed in the user mode. However, because the V
R
4101
always operates in little endian, fix the RX bit to 0 (reversing is prohibited).
4.4.4 Bootstrap exception vector (BEV)
The BEV bit is used to generate an exception while the correct operations of the cache and main memory are tested
during self-diagnosis. At reset and on occurrence of the NMI exception, BEV is automatically set to 1.
When the BEV bit of the status register is set, the TLB non-coincidence exception vector is changed to virtual address
0xFFFF FFFF BFC0 0200, and the general exception vector is changed to address 0xFFFF FFFF BFC0 0380.
When the BEV bit is cleared, the TLB non-coincidence exception vector is changed to 0xFFFF FFFF 8000 0000, and
the general exception vector is changed to 0xFFFF FFFF 8000 0180.
4.4.5 Cache error check
When the CE bit of the status register is set, the contents of the parity error register are written to the parity bit of the
data cache instead of the parity generated by the store instruction when the store instruction is executed. If Fill of the
CACHE instruction is executed, the contents of the parity error register are written to the parity bit of the instruction
cache instead of the instruction parity.
4.4.6 Inhibiting parity error
When the DE bit of the status register is set, the processor does not generate the cache parity error exception.
4.4.7 Enabling interrupts (IE)
When the IE bit of the status register is cleared, all the interrupts, except reset and non-maskable interrupt, are
disabled.
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