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參數(shù)資料
| 型號： | μPDPD30101 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-Bit Micro[rocessor(64位微處理器) |
| 中文描述： | 64位微[rocessor（64位微處理器） |
| 文件頁數(shù)： | 30/97頁 |
| 文件大?。?/td> | 409K |
| 代理商： | ΜPDPD30101 |
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μ
PD30101
29
Figure 3-14. Format of Data Cache
128 127
144 143
165
169 168
167 166
63
0
1
1
1
1
22
16
128
PTag
DataP
Data
0
W’
W
P
V
W’
W
P
V
PTag
DataP
Data
: Even parity for write back bit
: Write back bit
: Even parity for physical tag and V bit
: Valid bit
: Physical tag (bits 31-10 of physical address)
: Even parity for data (1-bit parity per 1-byte data)
: Cache data
3.8 Exception Processing
The V
R
4101 enters the kernel mode in which interrupts are disabled when an exception occurs, and executes an
exception handler from a fixed exception vector address. To restore from the exception, the program counter, operating
mode, and interrupt enable information must be restored to the original status. Save this information when the interrupt
occurs.
When an interrupt occurs, the EPC register holds the address of the instruction that has caused the exception, or the
address of the instruction immediately before if the exception has occurred in the branch delay slot. This means that the
EPC register stores the address from which execution is to be started after the exception has been processed. At reset
and on occurrence of NMI, the EPC register holds a restart address.
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