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參數(shù)資料
| 型號： | μPDPD30101 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-Bit Micro[rocessor(64位微處理器) |
| 中文描述： | 64位微[rocessor（64位微處理器） |
| 文件頁數(shù)： | 37/97頁 |
| 文件大?。?/td> | 409K |
| 代理商： | ΜPDPD30101 |
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μ
PD30101
36
Figure 4-5. HALTimer Shutdown
POWER
POWERON
MPOWER
ColdReset
(internal)
Reset
(internal)
PLL
(internal)
RTC
(internal, 32.768 kHz)
Stable oscillation
Stop
4s
>32 ms
7RTC
350 ms
8 ms
16 MasterClock
Note
Undefined
MRAS (0 : 3)/
UCAS/LCAS
Stable oscillation
Note
MasterClock is the basic clock in the CPU core.
4.3 PowerOn Sequence
The causes that change the status of the V
R
4101 from the Hibernate mode or shutdown status to the Fullspeed mode
are called start causes. The start causes include asserting the POWERON pin active, asserting the DCD pin active, and
alarm from the WakeUp timer. When a start cause occurs, the V
R
4101 asserts the POWERON pin active to inform the
external circuit that power to the V
R
4101 is about to be turned ON. Three RTC clocks after the POWERON pin has been
asserted active, the V
R
4101 checks the status of the BATTINH and GPIO9 (BATTLOCK) pins. When the BATTINH or
GPIO9 (BATTLOCK) pin is low, the V
R
4101 deasserts the POWERON pin inactive one RTC clock after checking the
BATTINH or GPIO9 pin status, and is not started. If both the BATTINH and GPIO9 (BATTCLOCK) pins are high, the
V
R
4101 deasserts the POWERON pin inactive four RTC clocks after the checking, asserts the MPOWER pin active, and
is started.
Figure 4-6 shows the timing chart where the V
R
4101 is started. Figure 4-7 shows the timing chart where the V
R
4101
is not started because the BATTINH pin is low.
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