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參數(shù)資料
| 型號： | μPDPD30101 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-Bit Micro[rocessor(64位微處理器) |
| 中文描述： | 64位微[rocessor（64位微處理器） |
| 文件頁數(shù)： | 60/97頁 |
| 文件大?。?/td> | 409K |
| 代理商： | ΜPDPD30101 |
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μ
PD30101
59
19. INSTRUCTION SET
Each instruction of the V
R
4101 consists of 1 word (32 bits) located at a word boundary. Three instruction formats are
available as shown in Figure 19-1. By employing the three simplified instruction formats, the decoding of instructions is
simplified. Complicated operations and addressing modes that are not frequently used are realized by the compiler.
19.1 Instruction Formats
The instruction formats of the V
R
4101 are shown below.
Figure 19-1. CPU Instruction Format
31
26 25
21 20
16 15
0
op
rs
rt
immediate
op
target
op
rs
rt
rd
sa
funct
31
26 25
0
31
26 25
21 20
16 15
0
11 10
6 5
I-type (immediate format)
J-type (jump format)
R-type (register format)
op
6-bit instruction code
rs
5-bit source register specifier
rt
5-bit target (source/destination) register, or conditional branch
immediate
16-bit immediate value, branch displacement, or address displacement
target
26-bit unconditional branch target address
rd
5-bit destination register specifier
sa
5-bit shift
funct
6-bit function field
19.2 CPU Instruction Set List
All the CPU instructions of the V
R
4101 are classified into three sets: instruction set common to all the V
R
series
processors (ISA: Instruction Set Architecture), instruction set executed by the V
R
4000 series (extended ISA), and system
control coprocessor instruction set. Each instruction set is listed below.
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