參數(shù)資料
型號(hào)： μPDPD30101
廠商： NEC Corp.
英文描述： 64-Bit Micro[rocessor(64位微處理器)
中文描述： 64位微[rocessor（64位微處理器）
文件頁(yè)數(shù)： 34/97頁(yè)
文件大小： 409K
代理商： ΜPDPD30101
μ
PD30101
33
4.2 CPU Core Registers at Reset
Each of the CPU core registers is reset as follows:
The TS and SR bits of the status register are cleared to 0.
The ERL and BEV bits of the status register are set to 1.
The upper-limit value (31) is set to the random register.
The wired register is initialized to 0.
Bits 31 through 28 of the config register are cleared to 0, and bits 22 through 3 are set to 0x04800. The other
bits are undefined.
The values of the registers other than above are undefined.
Figures 4-1 through 4-5 show the timing of RTC reset, RSTSW, Deadman’s SW, software shutdown, and HALTimer
shutdown.
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