參數(shù)資料
型號： μPDPD30101
廠商： NEC Corp.
英文描述： 64-Bit Micro[rocessor(64位微處理器)
中文描述： 64位微[rocessor（64位微處理器）
文件頁數(shù)： 63/97頁
文件大?。?/td> 409K
代理商： ΜPDPD30101
μ
PD30101
62
Table 19-2. CPU Instruction Set: Extended ISA (1/2)
Instruction
Description
Format
Load/store instruction
op
base
rt
offset
LD
Load Doubleword
LD
rt, offset (base)
LDL
Load Doubleword Left
LDL
rt, offset (base)
LDR
Load Doubleword Right
LDR
rt, offset (base)
LWU
Load Word Unsigned
LWU
rt, offset (base)
SD
Store Doubleword
SD
rt, offset (base)
SDL
Store Doubleword Left
SDL
rt, offset (base)
SDR
Store Doubleword Right
SDR
rt, offset (base)
AIU immediate instruction
op
rs
rt
immediate
DADDI
Doubleword Add Immediate
DADDI
rt, rs, immediate
DADDIU
Doubleword Add Immediate Unsigned
DADDIU
rt, rs, immediate
3-operand type instruction
op
rs
rt
rd
sa
funct
DADD
Doubleword Add
DADD
rd, rs, rt
DADDU
Doubleword Add Unsigned
DADDU
rd, rs, rt
DSUB
Doubleword Subtract
DSUB
rd, rs, rt
DSUBU
Doubleword Subtract Unsigned
DSUBU
rd, rs, rt
Shift instruction
op
rs
rt
rd
sa
funct
DSLL
Doubleword Shift Left Logical
DSLL
rd, rt, sa
DSRL
Doubleword Shift Right Logical
DSRL
rd, rt, sa
DSRA
Doubleword Shift Right Arithmetic
DSRA
rd, rt, sa
DSLLV
Doubleword Shift Left Logical Variable
DSLLV
rd, rt, rs
DSRLV
Doubleword Shift Right Logical Variable
DSRLV
rd, rt, rs
DSRAV
Doubleword Shift Right Arithmetic Variable
DSRAV
rd, rt, rs
DSLL32
Doubleword Shift Left Logical+32
DSLL32
rd, rt, sa
DSRL32
Doubleword Shift Right Logical+32
DSRL32
rd, rt, sa
DSRA32
Doubleword Shift Right Arithmetic+32
DSRA32
rd, rt, sa
Multiplication/division instruction (1)
op
rs
rt
rd
sa
funct
DMULT
Doubleword Multiply
DMULT
rs, rt
DMULTU
Doubleword Multiply Unsigned
DMULTU
rs, rt
DDIV
Doubleword Divide
DDIV
rs, rt
DDIVU
Doubleword Divide Unsigned
DDIVU
rs, rt
Multiplication/division instruction (2)
op
rs
rt
rd
sa
funct
MADD16
Multiply and Add 16-bit Integer
MADD16
rs, rt
DMADD16
Doubleword Multiply and Add 16-bit Integer
DMADD16 rs, rt
Branch instruction (1)
op
rs
rt
offset
BEQL
Branch On Equal Likely
BEQL
rs, rt, offset
BNEL
Branch On Not Equal Likely
BNEL
rs, rt, offset
BLEZL
Branch On Less Than Or Equal To Zero Likely
BLEZL
rs, offset
BGTZL
Branch On Greatrer Than Zero Likely
BGTZL
rs, offset
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