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參數(shù)資料
| 型號： | μPDPD30101 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-Bit Micro[rocessor(64位微處理器) |
| 中文描述： | 64位微[rocessor（64位微處理器） |
| 文件頁數(shù)： | 39/97頁 |
| 文件大?。?/td> | 409K |
| 代理商： | ΜPDPD30101 |
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μ
PD30101
38
4.4 Modes of V
R
4101
The V
R
4101 supports various modes which can be selected by the user. The mode of the CPU core is specified by
writing data to the status register and config register. The mode of the internal peripheral circuits is specified by writing
data to the I/O register.
This section explains the operation modes of the CPU.
4.4.1 Power mode
The V
R
4101 supports four power modes: Fullspeed, Standby, Suspend, and Hibernate.
(1) Fullspeed mode
Normally, the processor clock (PClock) operates at 33 MHz. The system bus clock operates at the same
rate as the PClock.
In the default status, the processor operates in the Fullspeed mode. After reset, it returns to the Fullspeed
mode.
(2) Standby mode
The processor can be set in the Standby mode when the STANDBY instruction is executed. In this mode,
all the internal clocks of the CPU core, except the timers and interrupts, are kept high. All the peripheral
units operate in the same manner as in the Fullspeed mode. Therefore, DMA operation can be executed
even in the Standby mode.
When the STANDBY instruction has completed the WB stage, the V
R
4101 stands by until the SysAD bus
(internal) enters the idle status. After that, the internal clock of the CPU core is shut down, and the pipeline
stops operating. However, the PLL, timers, interrupt clock, and internal bus clocks (TClock and MasterOut)
continue operating.
The processor in the standby mode returns to the Fullspeed mode when an interrupt, including the internally
generated timer interrupt, occurs.
(3) Suspend mode
The processor can be set in the Suspend mode when the SUSPEND instruction is executed. In this mode,
the processor stalls the pipeline and keeps all the internal clocks, except the PLL and interrupts, high. Supply
of TClock to the peripheral units is stopped. Therefore, the peripheral units, except specific interrupt units
(such as the one that controls the DCD pin), cannot operate. In this status, the contents of the registers
and cache are retained.
When the SUSPEND instruction has completed the WB stage, the V
R
4101 places the DRAM in the self-
refresh mode and stands by until the internal SysAD bus enters the idle status. After that, the internal clock
of the CPU core is shut down, and the pipeline continues operating. Supply of TClock to the peripheral units
is stopped. However, the PLL, timers, interrupt clock, and internal bus clocks (TClock and MasterOut)
continue operating.
The processor remains in the Suspend mode until it accepts an interrupt. When the processor accepts an
interrupt, it returns to the Fullspeed mode.
(4) Hibernate mode
The processor can be set in the Hibernate mode when the HIBERNATE instruction is executed. In this mode,
the processor stops supply of the clock to all the units. In this status, the contents of the registers and cache
are retained, and output of TClock and MasterOut is stopped.
The processor remains in the Hibernate mode until the POWER pin is asserted active or the WakeUp timer
interrupt occurs. If the POWER pin is asserted active, if the WakeUp timer interrupt occurs, or if the DCD
pin is asserted active, the processor returns to the Fullspeed mode. The power consumption in this mode
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