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參數(shù)資料
| 型號(hào)： | μPDPD30101 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-Bit Micro[rocessor(64位微處理器) |
| 中文描述： | 64位微[rocessor（64位微處理器） |
| 文件頁數(shù)： | 65/97頁 |
| 文件大?。?/td> | 409K |
| 代理商： | ΜPDPD30101 |
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μ
PD30101
64
19.3 Instruction Execution Time
In principle, the V
R
4101 executes one instruction in one cycle, but some instructions take two cycles or more.
(1) The data loaded by a load instruction cannot be used in the delay slot. If an instruction that uses load
data is placed in the delay slot, the pipeline stalls.
A store instruction stalls by the delay slot if it is followed by a load instruction or MFC0.
If a branch instruction whose condition is satisfied or a jump instruction is executed, the instruction at
the destination address is executed after the delay slot.
Table 19-4. Number of Delay Slot Cycles
Instruction Category
Necessary Number of Cycles (PCycle)
Load
1
Store
1
Jump
1
Branch
1
(2) The number of cycles indicated in the table below is necessary for executing an integer multiplication/
division or sum-of-products operation instruction.
These instructions can be executed in parallel with other instructions, except those that access the HI/
LO registers that store the result of an operation, and multiplication/division or sum-of-products operation
instruction.
Table 19-5. Number of Execution Cycles of Integer Multiplication/Division Instructions
Instruction Category
Necessary Number of Cycles (PCycle)
MULT
1
MULTU
1
DIV
35
DIVU
35
DMULT
4
DMULTU
4
DDIV
67
DDIVU
67
MADD16
1
DMADD16
1
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