參數(shù)資料
型號(hào)： μPDPD30101
廠商： NEC Corp.
英文描述： 64-Bit Micro[rocessor(64位微處理器)
中文描述： 64位微[rocessor（64位微處理器）
文件頁(yè)數(shù)： 33/97頁(yè)
文件大?。?/td> 409K
代理商： ΜPDPD30101
μ
PD30101
32
4. INITIALIZATION INTERFACE
This section explains the initialization interface and processor mode. Also explained are reset signal description and
type, dependency of signals and timing, and initialization sequence in the mode the user can select.
4.1 Reset Function
The V
R
4101 can be reset in the following five ways. For details, refer to the
V
R
4101 User’s Manual
.
4.1.1 RTC reset
Assert the RTCRST pin active on power application.
RTC reset does not save the status information at all, and completely initializes the internal status of the processor.
Because the DRAM does not enter the self-refresh mode, the contents of the DRAM after RTC reset are not guaranteed.
After reset, the processor serves as the master of the system bus, the sequence of the cold reset exception is
executed, and accessing the reset vector in the ROM space is started. Because only part of the internal status of the
V
R
4101 is reset, completely initialize the processor in software.
4.1.2 RSTSW
Assert the RSTSW pin active.
Reset by RSTSW initializes all the internal statuses except the RTC timer and PMU. Because the DRAM does not
enter the self-refresh mode, the contents of the DRAM after RSTSW reset are not guaranteed.
After reset, the processor serves as the master of the system bus, the sequence of the cold reset exception is
executed, and accessing the reset vector in the ROM space is started. Because only part of the internal status of the
V
R
4101 is reset, completely initialize the processor in software.
4.1.3 Deadman’s SW
The V
R
4101 is reset if Deadman’s SW is not cleared within a specific time after Deadman’s SW was enabled.
Reset by Deadman’s SW initializes all the internal statuses except the RTC timer and PMU. Because the DRAM
does not enter the self-refresh mode, the contents of the DRAM after Deadman’s SW reset are not guaranteed.
After reset, the processor serves as the master of the system bus, the sequence of the cold reset exception is
executed, and accessing the reset vector in the ROM space is started. Because only part of the internal status of the
V
R
4101 is reset, completely initialize the processor in software.
4.1.4 Software shutdown
When the software executes the HIBERNATE instruction, the V
R
4101 places the DRAM in the self-refresh mode,
deasserts the MPOWER pin inactive, and enters the reset status.
Reset by software shutdown initializes all the internal statuses except the RTC timer and PMU.
After reset, the processor serves as the master of the system bus, the sequence of the cold reset exception is
executed, and accessing the reset vector in the ROM space is started. Because only part of the internal status of the
V
R
4101 is reset, completely initialize the processor in software.
4.1.5 HALTimer shutdown
The V
R
4101 enters the reset status if HALTimer is not cleared by software within 4 seconds after RTC reset has been
cleared.
Reset by HALTimer initializes all the internal statuses except the RTC timer and PMU.
After reset, the processor serves as the master of the system bus, the sequence of the cold reset exception is
executed, and accessing the reset vector in the ROM space is started. Because only part of the internal status of the
V
R
4101 is reset, completely initialize the processor in software.
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