參數(shù)資料
型號(hào)： μPDPD30101
廠商： NEC Corp.
英文描述： 64-Bit Micro[rocessor(64位微處理器)
中文描述： 64位微[rocessor（64位微處理器）
文件頁(yè)數(shù)： 73/97頁(yè)
文件大?。?/td> 409K
代理商： ΜPDPD30101
μ
PD30101
72
(4) EDO type DRAM read parameter (1/2)
The target DRAM is the
μ
PD42S16165L-A70 or
μ
PD42S18165L-A70.
Parameter
Symbol
Condition
MIN.
MAX.
Unit
MRAS (0:3) pulse width
t
RASP
70
ns
MRAS (0:3) hold time (vs. UCAS/LCAS precharge)
t
RHCP
40
ns
MRAS (0:3) precharge time
t
RP
50
ns
MRAS (0:3) hold time (vs. UCAS/LCAS
↓
)
MRAS (0:3)
↓ →
LCAS/UCAS
↓
delay time
MRAS (0:3)
↓ →
UCAS/LCAS
↓
access time
MRAS (0:3)
↓ →
column address delay time
UCAS/LCAS hold time (vs. MRAS (0:3)
↓
)
t
RSH
12
ns
t
RCD
14
ns
t
RAC
95
ns
t
RAD
12
ns
t
CSH
50
ns
UCAS/LCAS pulse width
t
HCAS
12
ns
UCAS/LCAS precharge time
t
CP
10
ns
UCAS/LCAS precharge
→
MRAS (0:3)
↑
access time
UCAS/LCAS
↓ →
UCAS/LCAS
↓
access time
Read cycle time
t
ACP
60
ns
t
CAC
43
ns
t
HPC
30
ns
Row address setup time (ADD (9:20)) (vs. MRAS (0:3)
↓
)
Row address hold time (vs. MRAS (0:3)
↓
)
Column address setup time (vs. UCAS/LCAS
↓
)
Column address setup time (vs. MRAS (0:3)
↑
)
Column address hold time 1 (vs. UCAS/LCAS
↓
)
Column address hold time 2 (vs. UCAS/LCAS
↓
)
Column address hold time 3 (vs. UCAS/LCAS
↓
)
Column address
→
UCAS/LCAS
↓
access time
RAMOE
↓ →
UCAS/LCAS
↓
access time
Data input setup time 1 (vs. UCAS/LCAS
↓
)
Data input hold time 1 (vs. UCAS/LCAS
↓
)
Data input setup time 2 (vs. MRAS (0:3)
↑
)
Data input hold time 2 (vs. MRAS (0:3)
↑
)
Notes 1.
Applies to addresses other than the last address during block access
2.
Applied to the last address during block access
t
ASR
0
ns
t
RAH
10
ns
t
ASC
0
ns
t
RAL
35
ns
t
CAH1
ADD (9:18)
Note 1
12
ns
t
CAH2
ADD (9:18)
Note 2
12
ns
t
CAH3
ADD (19:20)
Note 2
12
ns
t
AA
60
ns
t
OEA
38
ns
t
DS1
20
ns
t
DH1
5
ns
t
DS2
20
ns
t
DH2
5
ns
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