參數(shù)資料
型號(hào)： μPDPD30101
廠商： NEC Corp.
英文描述： 64-Bit Micro[rocessor(64位微處理器)
中文描述： 64位微[rocessor（64位微處理器）
文件頁數(shù)： 6/97頁
文件大?。?/td> 409K
代理商： ΜPDPD30101
μ
PD30101
5
TABLE OF CONTENTS
1.
PIN FUNCTIONS.........................................................................................................................
1.1
Pin Functions.....................................................................................................................................
1.2
Pin Status in Specific Status............................................................................................................
8
8
12
2.
INTERNAL BLOCKS .................................................................................................................. 14
2.1
V
R
4100 CPU Core ..............................................................................................................................
2.2
BCU (Bus Control Unit).....................................................................................................................
2.3
RTC (Real-time Clock).......................................................................................................................
2.4
DSU (Deadman’s Switch Unit)..........................................................................................................
2.5
ICU (Interrupt Control Unit) ..............................................................................................................
2.6
PMU (Power Management Unit) .......................................................................................................
2.7
DMAAU (Direct Memory Access Address Unit) .............................................................................
2.8
DCU (Direct Memory Access Control Unit).....................................................................................
2.9
CMU (Clock Mask Unit) .....................................................................................................................
2.10 GIU (General Purpose I/O Unit) ........................................................................................................
2.11 AIU (Audio Interface Unit).................................................................................................................
2.12 KIU (Keyboard Interface Unit) ..........................................................................................................
2.13 PIU (Touch Panel Interface Unit)......................................................................................................
2.14 DebugSIU (Debug Serial Interface Unit)..........................................................................................
2.15 SIU (Serial Interface Unit) .................................................................................................................
14
14
14
14
14
15
15
15
15
15
15
15
15
15
15
3.
INTERNAL ARCHITECTURE ..................................................................................................... 16
3.1
Pipeline...............................................................................................................................................
3.2
CPU Registers ...................................................................................................................................
3.3
Outline of Instruction Set .................................................................................................................
3.4
System Control Coprocessor (CP0) ................................................................................................
3.4.1
CP0 registers .......................................................................................................................... 20
3.5
Data Format and Addressing ...........................................................................................................
3.6
Virtual Storage...................................................................................................................................
3.6.1
Virtual address space.............................................................................................................. 23
3.6.2
Address translation ................................................................................................................. 26
3.7
Cache..................................................................................................................................................
3.8
Exception Processing.......................................................................................................................
16
17
18
20
22
23
28
29
4.
INITIALIZATION INTERFACE .................................................................................................... 32
4.1
Reset Function ..................................................................................................................................
4.1.1
RTC reset................................................................................................................................ 32
4.1.2
RSTSW ................................................................................................................................... 32
4.1.3
Deadman’s SW ....................................................................................................................... 32
4.1.4
Software shutdown.................................................................................................................. 32
4.1.5
HALTimer shutdown................................................................................................................ 32
4.2
CPU Core Registers at Reset ...........................................................................................................
4.3
PowerOn Sequence...........................................................................................................................
4.4
Modes of V
R
4101 ...............................................................................................................................
32
33
36
38
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