參數(shù)資料
型號(hào)： 20736
英文描述： Enhanced Am486DX Family Data Sheet? 1.87MB (PDF)
中文描述： 增強(qiáng)Am486DX系列數(shù)據(jù)手冊(cè)？ 1.87MB（PDF格式）
文件頁數(shù)： 52/66頁
文件大小： 1923K
代理商： 20736
52
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
If WB/WT meets the necessary setup timing and is sam-
pled Low on the falling edge of RESET, the processor
is placed in Write-through mode and the test register
function is identical to Am486 microprocessors. If WB/
WT meets the necessary setup timing and is sampled
High on the falling edge of RESET, the processor is
placed in Write-back mode and the test registers TR4
and TR5 are modified to support the added write-back
cache functionality. Tables 18 and 19 show the individ-
ual bit functions of these registers. Sections 8.1 and 8.2
provide a detailed description of the field functions.
Note:
TR3 has he same unctions n both Write-through
and Write-back modes.These functions are identical to
the TR3 register functions provided by Am486 micro-
processors.
7.1
TR4 Definition
This section includes a detailed description of the bit
fields defined for TR4.
Note:
Bits listed in Table 18 as Reserved or Not used
are not included in these descriptions.
I
Tag (bits 31–12):
Read/Write, always available in
Write-through mode. Available only when EXT=0 in
TR5 in Write-back mode. For a cache write, this is
the tag that specifies the address in memory. On a
cache look-up, this is tag for the selected entry in the
cache.
I
STn (bits 30–29):
Read Only, available only in Write-
back mode when Ext=1 in TR5. STn returns the sta-
tus of the set (ST3, ST2, ST1, or ST0) specified by
the TR5 Set State field (bits 18–17) during cache
look-ups. Returned values are
— 00 = invalid
— 01 = exclusive
— 10 = modified
— 11 = shared
I
ST3 (bits 27–26):
Read Only, available only in Write-
back mode when Ext=1 in TR5. ST3 returns the sta-
tus of Set 3 during cache look-ups. Returned values
are
— 00 = invalid
— 01 = exclusive
— 10 = modified
— 11 = shared
I
ST2 (bits 25–24):
Read Only, available only in Write-
back mode when Ext=1 in TR5. ST2 returns the sta-
tus of Set 2 during cache look-ups. Returned values
are
— 00 = invalid
— 01 = exclusive
— 10 = modified
— 11 = shared
I
ST1 (bits 23–22):
Read Only, available only in Write-
back mode when Ext=1 in TR5. ST1 returns the sta-
tus of Set 1 during cache look-ups. Returned values
are
— 00 = invalid
— 01 = exclusive
— 10 = modified
— 11 = shared
I
ST0 (bits 21–20):
Read Only, available only in Write-
back mode when Ext=1 in TR5. ST0 returns the sta-
tus of Set 0 during cache look-ups. Returned values
are
— 00 = invalid
— 01 = exclusive
— 10 = modified
— 11 = shared
Table 18. Test Register TR4 Bit Descriptions
27–26
25–24
23–22
21–20
31
30–29
28
19–16
15–12
11
10
9–7
6–3
2–0
EXT=0
Tag
0
Valid
LRU
Valid
(rd)
Not
used
EXT=1
Not
used
STn
Rsvd.
ST3
ST2
ST1
ST0
Reserved
Not used
Valid
LRU
Valid
(rd)
Not
used
Table 19. Test Register TR5 Bit Descriptions
31–20
19
18–17
16
15–12
11–4
3–2
1–0
Write-Back
Not used
Ext
Set State
Reserved
Not used
Index
Entry
Control
Write-Through
Notes:
1. Bit 19 in TR5 is EXT. If EXT = 0, TR4 has the
standard 486
processor definition for write-through cache.
2. The values of Set State are: 00 = Invalid; 01 = Exclusive; 10 = Modified; 11 = Shared.
Not used
Index
Entry
Control
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