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| 型號： | 20736 |
| 英文描述： | Enhanced Am486DX Family Data Sheet? 1.87MB (PDF) |
| 中文描述： | 增強(qiáng)Am486DX系列數(shù)據(jù)手冊？ 1.87MB（PDF格式） |
| 文件頁數(shù)： | 38/66頁 |
| 文件大?。?/td> | 1923K |
| 代理商： | 20736 |
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38
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
4.5.3
Stop Clock state is entered from the Stop Grant state
by stopping the CLK input (either logic High or logic
Low). None of the CPU input signals should change
state while the CLK input is stopped. Any transition on
an input signal (except INTR) before the CPU has re-
turned to the Stop Grant state may result in unpredict-
able behavior. If INTR goes active while the CLK input
is stopped, and stays active until the CPU issues an
interrupt acknowledge bus cycle, it is serviced in the
normal manner. System design must ensure the CPU
is in the correct state prior to asserting cache invalidation
or interrupt signals to the CPU.
Stop Clock State
4.5.4
A HALT instruction causes the CPU to enter the Auto
HALT Power Down state. The CPU issues a normal
HALT bus cycle, and only transitions to the Normal state
when INTR, NMI, SMI, RESET, or SRESET occurs.
Auto Halt Power Down State
The system can generate a STPCLK while the CPU is
in the Auto HALT Power Down state. The CPU gener-
ates a Stop Grant bus cycle when it enters the Stop
Grant state from the HALT state. When the system deas-
serts the STPCLK interrupt, the CPU returns execution
to the HALT state. The CPU generates a new HALT bus
cycle when it re-enters the HALT state from the Stop
Grant state.
4.5.5
Stop Clock Snoop State
(Cache Invalidations)
When the CPU is in the Stop Grant state or the Auto
HALT Power Down state, the CPU recognizes HOLD,
AHOLD, BOFF, and EADS for cache invalidation. When
the system asserts HOLD, AHOLD, or BOFF, the CPU
floats the bus accordingly. When the system asserts
EADS, the CPU transparently enters Stop Clock Snoop
state and powers up for one full clock to perform the
required cache snoop cycle. If a modified line is
snooped, a cache write-back occurs with HITM transi-
tioning active until the completion of the write-back. It
then powers down and returns to the previous state. The
CPU does not generate a bus cycle when it returns to
the previous state.
4.5.6
When configured in Write-back mode, the processor
recognizes FLUSH for copying back modified cache
lines to memory in the Auto Halt Power Down State or
Normal State. Upon the completion of the cache flush,
the processor returns to its prior state, and regenerates
a special bus cycle, if necessary.
Cache Flush State
5
The Enhanced Am486DX microprocessors support a
soft reset function through the SRESET pin. SRESET
forces the processor to begin execution in a known state.
The processor state after SRESET is the same as after
SRESET FUNCTION
RESET except that the internal caches, CD and NW in
CR0, write buffers, SMBASE registers, and floating-
point registers retain the values they had prior to SRE-
SET, and cache snooping is allowed. The processor
starts execution at physical address FFFFFFF0h. SRE-
SET can be used to help performance for DOS extend-
ers written for the 80286 processor. SRESET provides
a method to switch from Protected to Real mode while
maintaining the internal caches, CR0, and the FPU
state. SRESET may not be used in place of RESET after
power-up.
In Write-back mode, once SRESET is sampled active,
the SRESET sequence begins on the next instruction
boundary (unless FLUSH or RESET occurs before that
boundary). When started, the SRESET sequence con-
tinues to completion and then normal processor execu-
tion resumes, independent of the deassertion of
SRESET. If a snoop hits a modified line during SRESET,
a normal write-back cycle occurs. ADS is asserted to
drive the bus cycles even if SRESET is not deasserted.
6
6.1
The Enhanced Am486DX microprocessors support four
modes: Real, Virtual, Protected, and System Manage-
ment mode (SMM).
As an operating mode, SMM has a
distinct processor environment, interface, and hard-
ware/software features. SMM lets the system designer
add new software-controlled features to the computer
products that always operate transparent to the operat-
ing system (OS) and software applications. SMM is in-
tended for use only by system firmware, not by
applications software or general-purpose systems soft-
ware.
SYSTEM MANAGEMENT MODE
Overview
The SMM architectural extension consists of the follow-
ing elements:
I
System Management Interrupt (SMI) hardware in-
terface
I
Dedicated and secure memory space (SMRAM) for
SMI handler code and CPU state (context) data with
a status signal for the system to decode access to
that memory space, SMIACT
I
Resume (RSM) instruction, for exiting SMM
I
Special features, such as I/O Restart and I/O instruc-
tion information, for transparent power management
of I/O peripherals, and Auto HALT Restart
6.2
Terminology
The following terms are used throughout the discussion
of System Management mode.
I
SMM:
System Management mode. The operating
environment that the processor (system) enters
when servicing a System Management Interrupt.
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