參數(shù)資料
型號(hào)： 20736
英文描述： Enhanced Am486DX Family Data Sheet? 1.87MB (PDF)
中文描述： 增強(qiáng)Am486DX系列數(shù)據(jù)手冊(cè)？ 1.87MB（PDF格式）
文件頁(yè)數(shù)： 40/66頁(yè)
文件大小： 1923K
代理商： 20736
40
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
6.3.1
SMI is a falling-edge-triggered, non-maskable interrupt
request signal. SMI is an asynchronous signal, but setup
and hold times must be met to guarantee recognition in
a specific clock. The SMI input does not have to remain
active until the interrupt is actually serviced. The SMI
input needs to remain active for only a single clock if the
required setup and hold times are met. SMI also works
correctly if it is held active for an arbitrary number of
clocks (see Figure 24).
System Management Interrupt Processing
The SMI input must be held inactive for at least four
clocks after it is asserted to reset the edge-triggered
logic. A subsequent SMI may not be recognized if the
SMI input is not held inactive for at least four clocks after
being asserted. SMI, like NMI, is not affected by the IF
bit in the EFLAGS register and is recognized on an in-
struction boundary. SMI does not break locked bus cy-
cles. SMI has a higher priority than NMI and is not
masked during an NMI. After SMI is recognized, the SMI
signal is masked internally until the RSM instruction is
executed and the interrupt service routine is complete.
Masking SMI prevents recursive calls. If another SMI
occurs while SMI is masked, the pending SMI is recog-
nized and executed on the next instruction boundary
after the current SMI completes. This instruction bound-
ary occurs before execution of the next instruction in the
interrupted application code, resulting in back-to-back
SMI handlers. Only one SMI signal can be pending while
SMI is masked. The SMI signal is synchronized inter-
nally and must be asserted at least three clock cycles
prior to asserting the RDY signal to guarantee recogni-
tion on a specific instruction boundary. This is important
for servicing an I/O trap with an SMI handler.
6.3.2
SMIACT indicates that the CPU is operating in SMM.
The CPU asserts SMIACT in response to an SMI inter-
rupt request on the SMI pin. SMIACT is driven active
after the CPU has completed all pending write cycles
(including emptying the write buffers), and before the
first access to SMRAM when the CPU saves (writes) its
state (or context) to SMRAM. SMIACT remains active
until the last access to SMRAM when the CPU restores
(reads) its state from SMRAM. The SMIACT signal does
not float in response to HOLD. The SMIACT signal is
used by the system logic to decode SMRAM. The num-
ber of clocks required to complete the SMM state save
and restore is dependent on system memory perfor-
mance. The values shown in Figure 25 assume 0 wait-
state memory writes (2 clock cycles), 2–1–1–1 burst
read cycles, and 0 wait-state non-burst reads (two clock
cycles). Additionally, it is assumed that the data read
during the SMM state restore sequence is not cache-
able. The minimum time required to enter a SMSAVE
SMI handler routine for the CPU (from the completion
of the interrupted instruction) is given by:
SMI Active (SMIACT)
Latency to start of SMl handler = A + B + C = 161 clocks
and the minimum time required to return to the interrupt-
ed application (following the final SMM instruction be-
fore RSM) is given by:
Latency to continue application = E + F + G = 258 clocks
CPU
SMIACT
SMI
SMI Interface
}
Figure 23. Basic SMI Hardware Interface
tsu
thd
SMI Sampled
CLK
CLK2
SMI
RDY
Figure 24. SMI Timing for Servicing an I/O Trap
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