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| 型號： | 20736 |
| 英文描述： | Enhanced Am486DX Family Data Sheet? 1.87MB (PDF) |
| 中文描述： | 增強(qiáng)Am486DX系列數(shù)據(jù)手冊？ 1.87MB（PDF格式） |
| 文件頁數(shù)： | 36/66頁 |
| 文件大?。?/td> | 1923K |
| 代理商： | 20736 |
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36
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
To achieve the lowest possible power consumption dur-
ing the Stop Grant state, the system designer must en-
sure that the input signals with pull-up resistors are not
driven Low, and the input signals with pull-down resis-
tors are not driven High.
All inputs except data bus pins must be driven to the
power supply rails to ensure the lowest possible current
consumption during Stop Grant or Stop Clock modes.
For compatibility, data pins must be driven Low to
achieve the lowest possible power consumption.
4.5
Figure 20 shows the state transitions during a Stop
Clock cycle.
Clock Control State Diagram
4.5.1
This is the normal operating state of the CPU. While in
the normal state, the CLK input can be dynamically
changed within the specified CLK period stability limits.
Normal State
4.5.2
The Stop Grant state provides a low-power state that
can be entered by simply asserting the external STPCLK
interrupt pin. When the Stop Grant bus cycle has been
placed on the bus, and either RDY or BRDY is returned,
the CPU is in this state. The CPU returns to the normal
execution state 10–20 clock cycles after STPCLK has
been deasserted.
Stop Grant State
While in the Stop Grant state, the pull-up resistors on
STPCLK and UP are disabled internally. The system
must continue to drive these inputs to the state they
were in immediately before the CPU entered the Stop
Grant State. For minimum CPU power consumption, all
other input pins should be driven to their inactive level
while the CPU is in the Stop Grant state.
A RESET or SRESET brings the CPU from the Stop
Grant state to the Normal state. The CPU recognizes
the inputs required for cache invalidations (HOLD,
AHOLD, BOFF, and EADS) as explained later. The CPU
does not recognize any other inputs while in the Stop
Grant state. Input signals to the
CPU are not recognized
until 1 clock after STPCLK is deasserted (see Figure 21).
While in the Stop Grant state, the CPU does not recog-
nize transitions on the interrupt signals (SMI, NMI, and
INTR). Driving an active edge on either SMI or NMI does
not guarantee recognition and service of the interrupt
request following exit from the Stop Grant state. How-
ever, if one of the interrupt signals (SMI, NMI, or INTR)
is driven active while the CPU is in the Stop Grant state,
and held active for at least one CLK after STPCLK is
deasserted, the corresponding interrupt will be serviced.
The Enhanced Am486DX microprocessors require
INTR to be held active until the CPU issues an interrupt
acknowledge cycle to guarantee recognition. This con-
dition also applies to the existing Am486 CPUs.
In the Stop Grant state, the system can stop or change
the CLK input. When the clock stops, the CPU enters
the Stop Clock state. The CPU returns to the Stop Grant
state immediately when the CLK input is restarted. You
must hold the STPCLK input Low until a stabilized fre-
quency has been maintained for at least 1 ms to ensure
that the PLL has had sufficient time to stabilize.
The CPU generates a Stop Grant bus cycle when en-
tering the state from the Normal or the Auto HALT Power
Down state. When the CPU enters the Stop Grant state
from the Stop Clock state or the Stop Clock Snoop state,
the CPU does not generate a Stop Grant bus cycle.
.
t
20
t
21
Figure 19. Entering Stop Grant State
RDY
ADDR
STPCLK
CLK
Stop Grant Bus cycle
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