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| 型號： | 20736 |
| 英文描述： | Enhanced Am486DX Family Data Sheet? 1.87MB (PDF) |
| 中文描述： | 增強Am486DX系列數(shù)據(jù)手冊？ 1.87MB（PDF格式） |
| 文件頁數(shù)： | 45/66頁 |
| 文件大?。?/td> | 1923K |
| 代理商： | 20736 |
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Enhanced Am486DX Microprocessor Family
45
P R E L I M I N A R Y
EFLAGS register (using the STI instruction). Software
interrupts are not blocked on entry to SMM, and the
system software designer must provide an SMM-com-
pliant interrupt handler before attempting to execute any
software interrupt instructions. Note that in SMM mode,
the interrupt vector table has the same properties and
location as the Real mode vector table.
NMI interrupts are blocked on entry to the SMI handler.
If an NMI request occurs during the SMI handler, it is
latched and serviced after the processor exits SMM.
Only one NMI request is latched during the SMI handler.
If an NMI request is pending when the processor exe-
cutes the RSM instruction, the NMI is serviced before
the next instruction of the interrupted code sequence.
Although NMI requests are blocked when the CPU en-
ters SMM, they may be enabled through software by
executing an IRET instruction. If the SMI handler re-
quires the use of NMI interrupts, it should invoke a dum-
my interrupt service routine to execute an IRET
instruction. When an IRET instruction is executed, NMI
interrupt requests are serviced in the same Real mode
manner in which they are handled outside of SMM.
6.7.2
The 32-bit SMM Revision Identifier specifies the version
of SMM and the extensions that are available on the
processor. The fields of the SMM Revision Identifiers
and bit definitions are shown in Table 14 and Table 15.
Bit 17 or 16 indicates whether the feature is supported
(1=supported, 0=not supported). The processor always
reads the SMM Revision Identifier at the time of a re-
store. The I/O Trap Extension and SMM Base Reloca-
SMM Revisions Identifier
tion bits are fixed. The processor writes these bits out
at the time it performs a save state.
Note:
Changing he state of he reserved bits may result
in unpredictable processor behavior.
6.7.3
Auto HALT Restart
The Auto HALT Restart slot at register offset (word lo-
cation) 7F02h in SMRAM indicates to the SMI handler
that the SMI interrupted the CPU during a HALT state;
bit 0 of slot 7F02h is set to 1 if the previous instruction
was a HALT (see Figure 28). If the SMI did not interrupt
the CPU in a HALT state, then the SMI microcode sets
bit 0 of the Auto HALT Restart slot to 0. If the previous
instruction was a HALT, the SMI handler can choose to
either set or reset bit 0. If this bit is set to 1, the RSM
microcode execution forces the processor to re-enter
the HALT state. If this bit is set to 0 when the RSM
instruction is executed, the processor continues execu-
tion with the instruction just after the interrupted HALT
instruction. If the HALT instruction is restarted, the CPU
will generate a memory access to fetch the HALT in-
struction (if it is not in the internal cache), and execute
a HALT bus cycle.
Table 16 shows the possible restart configurations. If
the interrupted instruction was not a HALT instruction
(bit 0 is set to 0 in the Auto HALT Restart slot upon SMM
entry), setting bit 0 to 1 will cause unpredictable behavior
when the RSM instruction is executed.
Table 14. SMM Revision Identifier
Table 15. SMM Revision Identifier Bit Definitions
HALT Auto Restart
Register Offset 7F02h
Reserved
15
1
0
Figure 28. Auto HALT Restart Register Offset
31–18
17
16
15–0
Reserved
SMM Base
Relocation
I/O Trap
Extension
SMM Revision Level
00000000000000
1
1
0000h
Bit Name
Description
Default
State
State at
SMM
Entry
State at
SMM Exit
Notes
SMM Base
Relocation
1=SMM Base Relocation Available
0=SMM Base Relocation
Unavailable
1
1
0
1
0
No Change in State
No Change in State
I/O Trap Extension
1=I/O Trapping Available
0=I/O Trapping Unavailable
1
1
0
1
0
No Change in State
No Change in State
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