Enhanced Am486DX Microprocessor Family
7
P R E L I M I N A R Y
LIST OF TABLES
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Clocking Options .................................................................................................................................... 1
CLKMUL Settings ................................................................................................................................. 13
EADS Sample Time ............................................................................................................................. 14
Cache Line Organization ..................................................................................................................... 18
Legal Cache Line States ...................................................................................................................... 18
MESI Cache Line Status ...................................................................................................................... 19
Key to Switching Waveforms ............................................................................................................... 21
WBINVD/INVD Special Bus Cycles ..................................................................................................... 32
FLUSH Special Bus Cycles ................................................................................................................. 32
Pin State During Stop Grant Bus State ................................................................................................ 35
SMRAM State Save Map ..................................................................................................................... 42
SMM Initial CPU Core Register Settings ............................................................................................. 44
Segment Register Initial States ............................................................................................................ 44
SMM Revision Identifier ....................................................................................................................... 45
SMM Revision Identifier Bit Definitions ................................................................................................ 45
HALT Auto Restart Configuration ........................................................................................................ 46
I/O Trap Word Configuration ................................................................................................................ 46
Test Register TR4 Bit Descriptions ...................................................................................................... 52
Test Register TR5 Bit Descriptions ...................................................................................................... 52
Am486 Family Functional Differences.................................................................................................. 54
CPU ID Codes ..................................................................................................................................... 55
CPUID Instruction Description ............................................................................................................. 55
Thermal Resistance (°C/W)
θ
JC
and
θ
JA
for the Enhanced Am486DX CPU in 168-Pin PGA Package 64
Maximum T
A
at Various Airflows in °C for Commercial Temperatures (85°C)...................................... 64
Maximum T
A
at Various Airflows in °C for Industrial Temperatures (100°C) ........................................ 64