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| 型號： | 20736 |
| 英文描述： | Enhanced Am486DX Family Data Sheet? 1.87MB (PDF) |
| 中文描述： | 增強Am486DX系列數(shù)據(jù)手冊？ 1.87MB（PDF格式） |
| 文件頁數(shù)： | 55/66頁 |
| 文件大小： | 1923K |
| 代理商： | 20736 |
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Enhanced Am486DX Microprocessor Family
55
P R E L I M I N A R Y
9
The Enhanced Am486DX microprocessors support two
standard methods for identifying the CPU in a system.
The reported values are assigned based on the RESET
status of the WB/WT pin input (Low = Write-through;
High = Write-back).
ENHANCED Am486DX CPU IDENTIFICATION
9.1
The DX register always contains a component identifier
at the conclusion of RESET. The upper byte of DX (DH)
contains 04 and the lower byte of DX (DL) contains a
CPU type/stepping identifier (see Table 21).
DX Register at RESET
9.2
The Enhanced Am486DX microprocessors implement
the CPUID instruction that makes information available
to software about the family, model and stepping of the
processor on which it is executing. Support of this in-
struction is indicated by the presence of a user-modifi-
able bit in position EFLAGS.21, referred to as the
EFLAGS.ID bit. This bit is reset to zero at device reset
(RESET or SRESET) for compatibility with existing pro-
cessor designs.
CPUID Instruction
9.2.1
CPUID execution timing depends on the selected EAX
parameter values (see Table 22).
CPUID Timing
9.2.2
The CPUID instruction requires the user to pass an input
parameter to the CPU in the EAX register. The CPU
response is returned to the user in registers EAX, EBX,
ECX, and EDX. When the parameter passed in EAX is
CPUID Operation
zero, the register values returned upon instruction exe-
cution are:
EAX[31:0]
EBX[31:0]
ECX[31:0]
EDX[31:0]
The values in EBX, ECX, and EDX indicate an AMD
microprocessor. When taken in the proper order:
I
EBX (least significant bit to most significant bit)
I
EDX (least significant bit to most significant bit)
I
ECX (least significant bit to most significant bit)
they decode to
AuthenticAMD
When the parameter passed in EAX is 1, the register
values returned are
EAX[3:0]
4h or 0100
EAX[7:4]
model:
Enhanced Am486DX CPU:
Write-through mode = Eh
Write-back mode = Fh
Family:
486 Instruction Set = 4h
EAX[15:12]
0000
EAX[31:16]
RESERVED
EBX[31:0]
00000000h
ECX[31:0]
00000000h
EDX[31:0]
00000001h = all versions
The 1 in bit 0 indicates that the FPU
is present
The value returned in EAX after CPUID instruction ex-
ecution is identical to the value loaded into EDX upon
device reset. Software must avoid any dependency
upon the state of reserved processor bits.
When the parameter passed in EAX is greater than one,
register values returned upon instruction execution are
Table 21. CPU ID Codes
Processor
CLKMUL
Write-
Back
Mode
0474h
0494h
04F4h
Write-
Through
Mode
0434h
0484h
04E4h
Am486DX2-66
Am486DX4-100
Am486DX5-133
0 (x2)
1 (x3)
0 (x4)
Table 22. CPUID Instruction Description
OP
Code
Instruction
EAX
Input
Value
0
1
>1
CPU
Core
Clocks
41
14
9
Description
0F A2 CPUID
AMD string
CPU ID Register
null registers
00000001h
68747541h
444D4163h
69746E65h
EAX[11:8]
EAX[31:0]
EBX[31:0]
ECX[31:0]
EDX[31:0]
Flags affected
: No flags are affected.
Exceptions
: None
00000000h
00000000h
00000000h
00000000h
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