參數(shù)資料
型號： 20736
英文描述： Enhanced Am486DX Family Data Sheet? 1.87MB (PDF)
中文描述： 增強Am486DX系列數(shù)據(jù)手冊？ 1.87MB（PDF格式）
文件頁數(shù)： 6/66頁
文件大?。?/td> 1923K
代理商： 20736
6
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
LIST OF FIGURES
Figure 1
Processor-Induced Line Transitions in Write-Back Mode .................................................................... 20
Figure 2
Snooping State Transitions .................................................................................................................. 20
Figure 3
Typical System Block Diagram for HOLD/HLDA Bus Arbitration ......................................................... 21
Figure 4
External Read ...................................................................................................................................... 22
Figure 5
External Write ...................................................................................................................................... 22
Figure 6
Snoop of On-Chip Cache That Does Not Hit a Line ............................................................................ 23
Figure 7
Snoop of On-Chip Cache That Hits a Non-Modified Line .................................................................... 24
Figure 8
Snoop That Hits a Modified Line (Write-Back) ..................................................................................... 24
Figure 9
Write-Back and Pending Access .......................................................................................................... 25
Figure 10 Valid HOLD Assertion During Write-Back ............................................................................................ 26
Figure 11 Closely Coupled Cache Block Diagram ............................................................................................... 27
Figure 12 Snoop Hit Cycle with Write-Back ......................................................................................................... 28
Figure 13 Cycle Reordering with BOFF (Write-Back) .......................................................................................... 29
Figure 14 Write Cycle Reordering Due to Buffering ............................................................................................. 30
Figure 15 Latest Snooping of Copy-Back ............................................................................................................ 32
Figure 16 Burst Write ........................................................................................................................................... 33
Figure 17 Burst Read with BOFF Assertion ......................................................................................................... 33
Figure 18 Burst Write with BOFF Assertion ......................................................................................................... 33
Figure 19 Entering Stop Grant State .................................................................................................................... 36
Figure 20 Stop Clock State Machine .................................................................................................................... 37
Figure 21 Recognition of Inputs when Exiting Stop Grant State .......................................................................... 37
Figure 22 Basic SMI Interrupt Service ................................................................................................................. 39
Figure 23 Basic SMI Hardware Interface.............................................................................................................. 40
Figure 24 SMI Timing for Servicing an I/O Trap ................................................................................................... 40
Figure 25 SMIACT Timing .................................................................................................................................... 41
Figure 26 Redirecting System Memory Address to SMRAM ............................................................................... 41
Figure 27 Transition to and from SMM ................................................................................................................. 43
Figure 28 Auto HALT Restart Register Offset....................................................................................................... 45
Figure 29 I/O Instruction Restart Register Offset ................................................................................................. 46
Figure 30 SMM Base Slot Offset .......................................................................................................................... 46
Figure 31 SRAM Usage ....................................................................................................................................... 47
Figure 32 SMRAM Location ................................................................................................................................. 47
Figure 33 SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Through Mode
with Caching Enabled During SMM...................................................................................................... 48
Figure 34 SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Back Mode
with Caching Enabled During SMM...................................................................................................... 48
Figure 35 SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Back Mode
with Caching Disabled During SMM ..................................................................................................... 48
Figure 36 SMM Timing in Systems Using Overlaid Memory Space and Write-Through Mode
with Caching Enabled During SMM...................................................................................................... 49
Figure 37 SMM Timing in Systems Using Overlaid Memory Space and Write-Through Mode
with Caching Disabled During SMM ..................................................................................................... 49
Figure 38 SMM Timing in Systems Using Overlaid Memory Space and Configured in Write-Back Mode ........... 49
Figure 39 CLK Waveforms ................................................................................................................................... 60
Figure 40 Output Valid Delay Timing ................................................................................................................... 60
Figure 41 Maximum Float Delay Timing .............................................................................................................. 61
Figure 42 PCHK Valid Delay Timing .................................................................................................................... 61
Figure 43 Input Setup and Hold Timing ............................................................................................................... 62
Figure 44 RDY and BRDY Input Setup and Hold Timing ..................................................................................... 62
Figure 45 TCK Waveforms ................................................................................................................................... 63
Figure 46 Test Signal Timing Diagram ................................................................................................................. 63
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