- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371362 > 20736 Enhanced Am486DX Family Data Sheet? 1.87MB (PDF) PDF資料下載
參數(shù)資料
| 型號： | 20736 |
| 英文描述： | Enhanced Am486DX Family Data Sheet? 1.87MB (PDF) |
| 中文描述： | 增強Am486DX系列數(shù)據(jù)手冊？ 1.87MB（PDF格式） |
| 文件頁數(shù)： | 28/66頁 |
| 文件大?。?/td> | 1923K |
| 代理商： | 20736 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁
28
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
3.8.6
Reordering of Write-Backs (AHOLD) with
BOFF
As seen previously, the Bus Interface Unit (BIU) com-
pletes the processor-initiated access first if the snooping
access occurs after the start of the processor-initiated
access. If the HITM signal occurs one clock cycle before
the ADS = 0 of the processor-initiated access, the write-
back receives priority and is executed first.
However, if the snooping access is executed after the
start of the processor-initiated access, there is a
methodology to reorder the access order. The BOFF
signal delays outstanding processor-initiated cycles so
that a snoop write-back can occur immediately (see
Figure 13).
Scenario
: If there are outstanding processor-initiated
cycles on the bus, asserting BOFF clears the bus pipe-
line. If a snoop causes HITM to be asserted, the first
cycle issued by the microprocessor after deassertion of
BOFF is the write-back cycle. After the write-back cycle,
it reissues the aborted cycles. This translates into the
following sequence:
Step 1 The processor starts a cacheable burst read
cycle.
Step 2 One clock cycle later, AHOLD is asserted. This
switches the address bus into an input one clock
cycle after AHOLD is asserted.
Step 3 Two clock cycles after AHOLD is asserted, the
EADS and INV signals are asserted to start the
snooping cycle.
Step 4 Two clock cycles after EADS is asserted, HITM
becomes valid. The line is modified, therefore
HITM = 0.
Step 5 Note that the processor-initiated access is not
completed because BLAST = 1.
Step 6 With HITM going Low, the core system logic
asserts BOFF in the next clock cycle to the
snooping processor to reorder the access.
BOFF overrides BRDY. Therefore, the partial
read is not used. It is reread later.
Step 7 One clock cycle later BOFF is deasserted. The
write-back access starts one clock cycle later
because the BOFF has cleared the bus pipe-
line.
Step 8 AHOLD is deasserted. In the next clock cycle
the address for the write-back is driven on the
address bus.
10
9
Data
HITM
EADS
INV
Read
BRDY
AHOLD
BLAST
ADS
W/R
M/IO
ADR
CLK
W n+4
W n
W n+8
W n+C
Figure 12. Snoop Hit Cycle with Write-Back
Note:
The circled numbers in this figure represent the steps in section 4.8.5.3.
1
7
8
5
4
6
3
2
CACHE
from CPU
to CPU
from CPU
相關PDF資料 |
PDF描述 |
|---|---|
| 2075 | data delay devices |
| 208-501-21-38 | LED TELEFONSOCKEL T6.8 12V ROT |
| 208-521-21-38 | LED TELEFONSOCKEL T6.8 12V GELB |
| 208-532-21-38 | LED TELEFONSOCKEL T6.8 12V GRUEN |
| 208-930-21-38 | LED TELEFONSOCKEL T6.8 12V BLAU |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 207360-1 | 功能描述:管腳和插座連接器 3P PLUG HOUSING RoHS:否 制造商:Molex 系列:1561 產品類型:Contacts 觸點類型:Socket (Female) 節(jié)距: 位置/觸點數(shù)量: 排數(shù): 安裝風格:Wire 端接類型:Crimp 外殼材料: 觸點材料:Brass 觸點電鍍:Tin 電壓額定值: 電流額定值: |
| 20-7360-10 | 功能描述:IC 與器件插座 ELEVATOR STRIP LINE 20 PINS RoHS:否 制造商:Molex 產品:LGA Sockets 節(jié)距:1.02 mm 排數(shù): 位置/觸點數(shù)量:2011 觸點電鍍:Gold 安裝風格:SMD/SMT 端接類型:Solder 插座/封裝類型:LGA 2011 工作溫度范圍:- 40 C to + 100 C |
| 207363-000 | 制造商:TE Connectivity 功能描述:MTC50-YH2-004 |
| 207365-1 | 功能描述:管腳和插座連接器 PIN HDR ASSY METRIMATE 3P RoHS:否 制造商:Molex 系列:1561 產品類型:Contacts 觸點類型:Socket (Female) 節(jié)距: 位置/觸點數(shù)量: 排數(shù): 安裝風格:Wire 端接類型:Crimp 外殼材料: 觸點材料:Brass 觸點電鍍:Tin 電壓額定值: 電流額定值: |
| 207365-3 | 功能描述:管腳和插座連接器 PIN HEADER 3P RoHS:否 制造商:Molex 系列:1561 產品類型:Contacts 觸點類型:Socket (Female) 節(jié)距: 位置/觸點數(shù)量: 排數(shù): 安裝風格:Wire 端接類型:Crimp 外殼材料: 觸點材料:Brass 觸點電鍍:Tin 電壓額定值: 電流額定值: |
發(fā)布緊急采購，3分鐘左右您將得到回復。