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| 型號： | 20736 |
| 英文描述： | Enhanced Am486DX Family Data Sheet? 1.87MB (PDF) |
| 中文描述： | 增強Am486DX系列數(shù)據(jù)手冊？ 1.87MB（PDF格式） |
| 文件頁數(shù)： | 35/66頁 |
| 文件大小： | 1923K |
| 代理商： | 20736 |
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Enhanced Am486DX Microprocessor Family
35
P R E L I M I N A R Y
I
Empties all internal pipelines and write buffers
I
Generates a Stop Grant bus cycle
I
Stops the internal clock
At this point the CPU is in the Stop Grant state.
The CPU cannot respond to a STPCLK request from an
HLDA state because it cannot empty the write buffers
and, therefore, cannot generate a Stop Grant cycle. The
rising edge of STPCLK signals the CPU to return to
program execution at the instruction following the inter-
rupted instruction. Unlike the normal interrupts (INTR
and NMI), STPCLK does not initiate interrupt acknowl-
edge cycles or interrupt table reads.
4.2.1
In Write-through mode, the priority order of external in-
terrupts is:
External Interrupts in Order of Priority
1.
2.
3.
4.
5.
6.
RESET/SRESET
FLUSH
SMI
NMI
INTR
STPCLK
In Write-back mode, the priority order of external inter-
rupts is:
1.
2.
3.
4.
5.
6.
7.
RESET
FLUSH
SRESET
SMI
NMI
INTR
STPCLK
STPCLK is active Low and has an internal pull-up re-
sistor. STPCLK is asynchronous, but setup and hold
times must be met to ensure recognition in any specific
clock. STPCLK must remain active until the Stop Grant
special bus cycle is asserted and the system responds
with either RDY or BRDY. When the CPU enters the
Stop Grant state, the internal pull-up resistor is disabled,
reducing the CPU power consumption. The STPCLK
input must be driven High (not floated) to exit the Stop
Grant state. STPCLK must be deasserted for a minimum
of five clocks after RDY or BRDY is returned active for
the Stop Grant bus cycle before being asserted again.
There are two regions for the Low-power mode supply
current:
1. Low Power: Stop Grant state (fast wake-up, frequency-
and voltage-dependent)
2. Lowest Power: Stop Clock state (slow wake-up, volt-
age-dependent)
4.3
The processor drives a special Stop Grant bus cycle to
the bus after recognizing the STPCLK interrupt. This
bus cycle is the same as the HALT cycle used by a
standard Am486 microprocessor, with the exception
that the Stop Grant bus cycle drives the value 0000
0010h on the address pins.
Stop Grant Bus Cycle
I
M/lO = 0
I
D/C = 0
I
W/R =1
I
Address Bus = 0000 0010h (A
4
= 1)
I
BE3
–BE0 = 1011
I
Data bus = undefined
The system hardware must acknowledge this cycle by
returning RDY or BRDY, or the processor will not enter
the Stop Grant state (see Figure 19). The latency be-
tween a STPCLK request and the Stop Grant bus cycle
depends on the current instruction, the amount of data
in the CPU write buffers, and the system memory per-
formance.
4.4
Table 10 shows the pin states during Stop Grant Bus
states. During the Stop Grant state, most output and
input/output signals of the microprocessor maintain the
level they held when entering the Stop Grant state. The
data and data parity signals are three-stated. In re-
sponse to HOLD being driven active during the Stop
Grant state (when the CLK input is running), the CPU
generates HLDA and three-states all output and input/
output signals that are three-stated during the HOLD/
HLDA state. After HOLD is deasserted, all signals return
to the same state they were before the HOLD/HLDA
sequence.
Pin State During Stop Grant
Table 10. Pin State During Stop Grant Bus State
Signal
Type
O
I/O
I/O
O
I/O
O
O
O
O
O
O
O
O
O
O
State
A3–A2
A31–A4
D31–D0
BE3–BE0
DP3–DP0
W/R, D/C, M/IO, CACHE
ADS
LOCK, PLOCK
BREQ
HLDA
BLAST
FERR
PCHK
SMIACT
HITM
Previous State
Previous State
Floated
Previous State
Floated
Previous State
Inactive
Inactive
Previous State
As per HOLD
Previous State
Previous State
Previous State
Previous State
Previous State
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